Сигнальный МП Motorola DSP56002 (1086189), страница 44
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These registers are illustrated inFigure 6-44 and Figure 6-45. The following paragraphs give detailed descriptions and operations of each of the bits in the SSI registers. The SSI registers are not prefaced withan “S” (for serial) as are the SCI registers.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 836 - 8413WL0(0)14TIE(0)15RIE(0)For More Information On This Product,Go to: www.freescale.comPORT C121210DC2(0)11109TDE(1)RDF(0)X:$FFEE6SYN(0)•7GCK(0)•MOD(0)9DC1(0)X:$FFEETE(0)11DC3(0)FRAME RATE DIVIDERCONTROLDC4(0)8775SHFD(0)645RFS(0)3PM3(0)4SCD2(0)3SCD1(0)2SCD0(0)2PM2(0)1OF1(0)1PM1(0)0OF0(0)0PM0(0)TFS(0)•2IF0(0)•0Figure 6-44 SSI Programming Model — Control and Status RegistersTRANSMITTER UNDERRUN ERROR FLAGRECEIVE FRAME SYNCSSI STATUS REGISTER (SSISR)(READ)SSI TIME SLOT REGISTER (TSR)(WRITE)SSI CONTROL REGISTER B (CRB)(READ/WRITE)SSI CONTROL REGISTER A (CRA)(READ/WRITE)TRANSMIT FRAME SYNCINPUT FLAGSIF1(0)•1GATED CLOCK CONTROLSYNC/ASYNC CONTROLFRAME SYNC LENGTH (BIT/WORD)FRAME SYNC LENGTH 0 (MIXED BIT/WORD)SHIFT DIRECTIONSERIAL CONTROL DIRECTION OUTPUT FLAGSSCKD(0)RESET VALUE = $40TUE(0)•34PM4(0)PRESCALE MODULUS SELECTPM5(0)RESET VALUE = $0000FSL0(0)•6PM6(0)RESET VALUE = $0000PM7(0)RECEIVER OVERRUN ERROR FLAGROE(0)•5FSL1(0)8DC0(0)TRANSMIT DATA REGISTER EMPTYRECEIVE DATA REGISTER FULLMODE SELECT (NETWORK/NORMAL)TRANSMITTER ENABLERECEIVER ENABLETRANSMIT INTERRUPT ENABLERE(0)13WORD-LENGTHCONTROLRECEIVE INTERRUPT ENABLEX:$FFEDPRESCALERANGEX:$FFEC14WL1(0)15PSR(0)Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)2316 15X:$FFEFRECEIVE HIGH BYTERECEIVE MIDDLE BYTE7023SERIALRECEIVESHIFTREGISTER8 70SERIAL RECEIVE DATA(RX) REGISTER(READ ONLY)RECEIVE LOW BYTE70 716 1508 7RECEIVE HIGH BYTERECEIVE MIDDLE BYTE0RECEIVE LOW BYTE24 BIT7070 7016 BIT12 BITSRDFreescale Semiconductor, Inc...8 BITWL1, WL0MSBLSB8-BIT DATA0MSB0LEAST SIGNIFICANTZERO FILL0LSB12-BIT DATALSBMSB16-BIT DATAMSBLSB24-BIT DATANOTES:1.
Data is received MSB first if SHFD = 0.2. Compatible with fractional format.(a) Receive Registers for SHFD = 0SERIAL RECEIVE SHIFT REGISTER23X:$FFEF16 15TRANSMIT HIGH BYTE7TRANSMIT MIDDLE BYTE0230 716 157MSB700 70MSBSERIAL TRANSMITSHIFT REGISTERTRANSMIT LOW BYTE0LSB8-BIT DATASERIAL TRANSMIT DATA(TX) REGISTER(WRITE ONLY)08 7TRANSMIT MIDDLE BYTE00TRANSMIT LOW BYTE7TRANSMIT HIGH BYTESTD8 70LEAST SIGNIFICANTZERO FILL0LSB12-BIT DATALSBMSB16-BIT DATAMSBLSB24-BIT DATANOTES:1. Data is sent MSB first if SHFD = 0.2. Compatible with fractional format.(b) Transmit Registers for SHFD = 0Figure 6-45 SSI Programming Model (Sheet 1 of 2)MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 85Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)2316 15X:$FFEFRECEIVE HIGH BYTERECEIVE MIDDLE BYTE702316 157RECEIVE HIGH BYTESRD07SERIAL RECEIVE DATA(RX) REGISTER(READ ONLY)0 708 70RECEIVE LOW BYTE0 7SERIAL RECEIVESHIFT REGISTER0LSB8-BIT DATA0MSBFreescale Semiconductor, Inc...0RECEIVE LOW BYTERECEIVE MIDDLE BYTE7MSB8 70LEAST SIGNIFICANTZERO FILL0LSB12-BIT DATALSBMSB16-BIT DATAMSBLSB24-BIT DATANOTES:1.
Data is received LSB first if SHFD = 1.2. Compatible with fractional format.(c) Receive Registers for SHFD = 123X:$FFEF16 15TRANSMIT HIGH BYTE8 7TRANSMIT MIDDLE BYTE0SERIAL TRANSMIT DATA(TX) REGISTER(READ ONLY)TRANSMIT LOW BYTE7070 702316 158 70TRANSMIT HIGH BYTE7TRANSMIT MIDDLE BYTE07TRANSMIT LOW BYTE0 7SERIAL TRANSMIT/SHIFTREGISTER024 BIT16 BIT12 BITSTD8 BITWL1, WL0MSBLSB8-BIT DATA0MSB0LEAST SIGNIFICANTZERO FILL0LSB12-BIT DATALSBMSB16-BIT DATAMSBLSB24-BIT DATANOTES:1.
Data is received LSB first if SHFD = 1.2. Compatible with fractional format.(d) Transmit Registers for SHFD = 1Figure 6-45 SSI Programming Model (Sheet 2 of 2)6 - 86PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.2.1SSI Control Register A (CRA)CRA is one of two 16-bit read/write control registers used to direct the operation of theSSI. The CRA controls the SSI clock generator bit and frame sync rates, word length, andnumber of words per frame for the serial data. The high-order bits of CRA are read as zeros by the DSP CPU. The CRA control bits are described in the following paragraphs.6.4.2.1.1CRA Prescale Modulus Select (PM7–PM0) Bits 0–7The PM0–PM7 bits specify the divide ratio of the prescale divider in the SSI clock generator.A divide ratio from 1 to 256 (PM=0 to $FF) may be selected.
The bit clock output is availableat the transmit clock (SCK) and/or the receive clock (SC0) pins of the DSP. The bit clockoutput is also available internally for use as the bit clock to shift the transmit and receiveshift registers. Careful choice of the crystal oscillator frequency and the prescaler moduluswill allow the industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz,and 1.536 MHz to be generated. Hardware and software reset clear PM0–PM7.6.4.2.1.2CRA Frame Rate Divider Control (DC4–DC0) Bits 8–12The DC4–DC0 bits control the divide ratio for the programmable frame rate dividers usedto generate the frame clocks (see Figure 6-43).
In network mode, this ratio may be interpreted as the number of words per frame minus one. In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (DC=00000 to11111) for normal mode and 2 to 32 (DC=00001 to 11111) for network mode.A divide ratio of one (DC=00000) in network mode is a special case (see 6.4.7.4).
In normal mode, a divide ratio of one (DC=00000) provides continuous periodic data word transfers. A bit-length sync (FSL1=1, FSL0=0) must be used in this case. Hardware and software reset clear DC4–DC0.6.4.2.1.3CRA Word Length Control (WL0, WL1) Bits 13 and 14The WL1 and WL0 bits are used to select the length of the data words being transferred via theSSI.
Word lengths of 8, 12, 16, or 24 bits may be selected according to Table 6-10.Table 6-10 Number of Bits/WordMOTOROLAWL1WL0Number of Bits/Word008011210161124PORT CFor More Information On This Product,Go to: www.freescale.com6 - 87Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...These bits control the number of active clock transitions in the gated clock modes andcontrol the word length divider (see Figure 6-42 and Figure 6-43), which is part of theframe rate signal generator for continuous clock modes.
The WL control bits also controlthe frame sync pulse length when FSL0 and FSL1 select a WL bit clock (see Figure 6-42).Hardware and software reset clear WL0 and WL1.6.4.2.1.4CRA Prescaler Range (PSR) Bit 15The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler.This bit is used to extend the range of the prescaler for those cases where a slower bitclock is desired (see Figure 6-42). When PSR is cleared, the fixed prescaler is bypassed.When PSR is set, the fixed divide-by-eight prescaler is operational. This allows a 128-kHzmaster clock to be generated for MC14550x series codecs.The maximum internally generated bit clock frequency is fosc/4, the minimum internallygenerated bit clock frequency is fosc/4/8/256=fosc/8192. Hardware and software resetclear PSR.6.4.2.2SSI Control Register B (CRB)The CRB is one of two 16-bit read/write control registers used to direct the operation ofthe SSI.
CRB controls the SSI multifunction pins, SC2, SC1, and SC0, which can be usedas clock inputs or outputs, frame synchronization pins, or serial I/O flag pins. The serialoutput flag control bits and the direction control bits for the serial control pins are in theSSI CRB.
Interrupt enable bits for each data register interrupt are provided in this controlregister. When read by the DSP, CRB appears on the two low-order bytes of the 24-bitword, and the high-order byte reads as zeros. Operating modes are also selected in thisregister. Hardware and software reset clear all the bits in the CRB. The relationships between the SSI pins (SC0, SC1, SC2, and SCK) and some of the CRB bits are summarizedin Tables Table 6-5, Table 6-12, and Table 6-13.
The SSI CRB bits are described in thefollowing paragraphs.6.4.2.2.1CRB Serial Output Flag 0 (OF0) Bit 0When the SSI is in the synchronous clock mode and the serial control direction zero bit(SCD0) is set, indicating that the SC0 pin is an output, then data present in OF0 will bewritten to SC0 at the beginning of the frame in normal mode or at the beginning of the nexttime slot in network mode. Hardware and software reset clear OF0.6.4.2.2.2CRB Serial Output Flag 1 (OF1) Bit 1When the SSI is in the synchronous clock mode and the serial control direction one6 - 88PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)(SCD1) bit is set, indicating that the SC1 pin is an output, then data present in OF1 will bewritten to the SC1 pin at the beginning of the frame in normal mode or at the beginning ofthe next time slot in network mode (see 6.4.7).Freescale Semiconductor, Inc...The normal sequence for setting output flags when transmitting data is to poll TDE (TXempty), to first write the flags, and then write the transmit data to the TX register.
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