Сигнальный МП Motorola DSP56002 (1086189), страница 46
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When the SSISR is read to the internal data bus, the register contents occupy the low-order byte of the data bus, and the high-order portion is zerofilled. The status bits are described in the following paragraphs.6.4.2.3.1SSISR Serial Input Flag 0 (IF0) Bit 0The SSI latches data present on the SC0 pin during reception of the first received bit afterframe sync is detected. IF0 is updated with this data when the receive shift register istransferred into the receive data register. The IF0 bit is enabled only when SCD0 iscleared and SYN is set, indicating that SC0 is an input and the synchronous mode is selected (see Table 6-5); otherwise, IF0 reads as a zero when it is not enabled.
Hardware,software, SSI individual, and STOP reset clear IF0.6.4.2.3.2SSISR Serial Input Flag 1 (IF1) Bit 1The SSI latches data present on the SC1 pin during reception of the first received bit afterframe sync is detected. The IF1 flag is updated with the data when the receiver shift register is transferred into the receive data register. The IF1 bit is enabled only when SCD1is cleared and SYN is set, indicating that SC1 is an input and the synchronous mode isselected (see Table 6-5); otherwise, IF1 reads as a zero when it is not enabled. Hardware,software, SSI individual, and STOP reset clear IF1.6.4.2.3.3SSISR Transmit Frame Sync Flag (TFS) Bit 2When set, TFS indicates that a transmit frame sync occurred in the current time slot.
TFSis set at the start of the first time slot in the frame and cleared during all other time slots.If word-wide transmit frame sync is selected (FSL0=FSL1), this indicates that the framesync was high at least at the beginning of the time slot if external frame sync is selected,or high throughout the time slot if internal frame sync was selected. If bit-wide transmitframe sync is selected (FSL0≠FSL1), this indicates that the frame sync (either internal orexternal) was high during the last Tx clock bit period prior to the current time slot, and thatthe frame sync falling edge corresponds to the assertion of the first output data bit, asshown below.Bit-Length FsWord-Length FsTime slotsTime slot #1Time slot #2Time slot #3Tx shift clockTFS set here6 - 94PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Data written to the transmit data register during the time slot when TFS is set will be transmitted (in network mode) during the second time slot in the frame.
TFS is useful in network modeto identify the start of the frame. This is illustrated in a typical transmit interrupt handler:MOVEPJCLRJMPX:(R4)+,X:SSITx#2,X:SSISR,_NoTFS;1 = FIRST TIMESLOT;Do something_DONE_NoTFS;Do something elseFreescale Semiconductor, Inc..._DONENote: In normal mode, TFS will always read as a one when transmitting data becausethere is only one time slot per frame – the “frame sync” time slot.TFS, which is cleared by hardware, software, SSI individual, or STOP reset, is notaffected by TE.6.4.2.3.4SSISR Receive Frame Sync Flag (RFS) Bit 3When set, RFS indicates that a receive frame sync occurred during reception of the wordin the serial receive data register.
This indicates that the data word is from the first timeslot in the frame. If word-wide receive frame sync is selected (FSL1=0), this indicates thatthe frame sync was high at least at the beginning of the timeslot. If bit-wide receive framesync is selected (FSL1=1), this indicates that the frame sync (either internal or external)was high during the last bit period prior to the current timeslot, and that the frame syncfalling edge corresponds to the assertion of the first output data bit, as shown below.Bit-Length FsWord-Length FsTime slotsTime slot #1Time slot #2Time slot #3Rx shift clockRFS set hereWhen RFS is clear and a word is received, it indicates (only in network mode) that theframe sync did not occur during reception of that word. RFS is useful in network mode toidentify the start of the frame.
This feature is illustrated in a typical receive interrupt handler:MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 95Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOVEPJCLRJMPX:SSIRx,X:(R4)+#3,X:SSISR,_NoRFS ;1 = FIRST TIMESLOT;Do something_DONE_NoRFS;Do something else_DONEFreescale Semiconductor, Inc...Note: In normal mode, RFS will always read as a one when reading data because thereis only one time slot per frame – the “frame sync” time slot.RFS, which is cleared by hardware, software, SSI individual, or STOP reset, is not affected by RE.6.4.2.3.5SSISR Transmitter Underrun Error Flag (TUE) Bit 4TUE is set when the serial transmit shift register is empty (no new data to be transmitted)and a transmit time slot occurs.
When a transmit underrun error occurs, the previous data(which is still present in the TX) will be retransmitted.In the normal mode, there is only one transmit time slot per frame. In the network mode,there can be up to 32 transmit time slots per frame.TUE does not cause any interrupts; however, TUE does cause a change in the interruptvector used for transmit interrupts so that a different interrupt handler may be used for atransmit underrun condition. If a transmit interrupt occurs with TUE set, the transmit datawith exception status interrupt will be generated; if a transmit interrupt occurs with TUEclear, the transmit data without errors interrupt will be generated.Hardware, software, SSI individual, and STOP reset clear TUE.
TUE is also cleared byreading the SSISR with TUE set, followed by writing TX or TSR.6.4.2.3.6SSISR Receiver Overrun Error Flag (ROE) Bit 5This flag is set when the serial receive shift register is filled and ready to transfer to thereceiver data register (RX) and RX is already full (i.e., RDF=1). The receiver shift registeris not transferred to RX. ROE does not cause any interrupts; however, ROE does causea change in the interrupt vector used for receive interrupts so that a different interrupt handler may be used for a receive error condition. If a receive interrupt occurs with ROE set,the receive data with exception status interrupt will be generated; if a receive interrupt occurs with ROE clear, the receive data without errors interrupt will be generated.Hardware, software, SSI individual, and STOP reset clear ROE. ROE is also cleared by reading the SSISR with ROE set, followed by reading the RX. Clearing RE does not affect ROE.6 - 96PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.2.3.7SSISR SSI Transmit Data Register Empty (TDE) Bit 6This flag is set when the contents of the transmit data register are transferred to the transmit shift register; it is also set for a disabled time slot period in network mode (as if datawere being transmitted after the TSR was written).
Thirdly, it can be set by the hardware,software, SSI individual, or STOP reset. When set, TDE indicates that data should be written to the TX or to the time slot register (TSR). TDE is cleared when the DSP writes to thetransmit data register or when the DSP writes to the TSR to disable transmission of thenext time slot. If TIE is set, a DSP transmit data interrupt request will be issued when TDEis set.
The vector of the interrupt will depend on the state of the transmitter underrun bit.6.4.2.3.8SSISR SSI Receive Data Register Full (RDF) Bit 7RDF is set when the contents of the receive shift register are transferred to the receivedata register. RDF is cleared when the DSP reads the receive data register or cleared byhardware, software, SSI individual, or STOP reset. If RIE is set, a DSP receive data interrupt request will be issued when RDF is set. The vector of the interrupt request will dependon the state of the receiver overrun bit.6.4.2.3.9SSI Receive Shift RegisterThis 24-bit shift register receives the incoming data from the serial receive data pin.
Datais shifted in by the selected (internal/external) bit clock when the associated frame syncI/O (or gated clock) is asserted. Data is assumed to be received MSB first if SHFD equalszero and LSB first if SHFD equals one. Data is transferred to the SSI receive data registerafter 8, 12, 16, or 24 bits have been shifted in, depending on the word-length control bitsin the CRA (see Figure 6-47).6.4.2.3.10SSI Receive Data Register (RX)RX is a 24-bit read-only register that accepts data from the receive shift register as it becomes full. The data read will occupy the most significant portion of the receive data register (see Figure 6-47).
The unused bits (least significant portion) will read as zeros. TheDSP is interrupted whenever RX becomes full if the associated interrupt is enabled.6.4.2.3.11SSI Transmit Shift RegisterThis 24-bit shift register contains the data being transmitted. Data is shifted out to the serial transmit data pin by the selected (internal/external) bit clock when the associatedframe sync I/O (or gated clock) is asserted. The number of bits shifted out before the shiftregister is considered empty and may be written to again can be 8, 12, 16, or 24 bits (determined by the word-length control bits in CRA). The data to be transmitted occupies themost significant portion of the shift register.
The unused portion of the register is ignored.Data is shifted out of this register MSB first if SHFD equals zero and LSB first if SHFDequals one (see Figure 6-48).MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 97Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)GDB2316 1512 11870Freescale Semiconductor, Inc...RX24 BITSRECEIVE SHIFTREGISTERSRDSHFD = 016 BITS12 BITS8 BITS(a) SHFD = 0GDB2316 151211870RXRECEIVE SHIFTREGISTERSRDSHFD = 1(b) SHFD = 1Figure 6-47 Receive Data Path6 - 98PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)GDB2316 15870TXFreescale Semiconductor, Inc...12 11TRANSMIT SHIFTREGISTERSTDSHFD = 0(a) SHFD = 0GDB2316 15870TX12 1124 BITSTRANSMIT SHIFTREGISTERSTDSHFD = 18 BIT12 BIT16 BIT(b) SHFD = 1Figure 6-48 Transmit Data PathMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 99Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.2.3.12SSI Transmit Data Register (TX)TX is a 24-bit write-only register.
Data to be transmitted is written into this register and isautomatically transferred to the transmit shift register. The data written (8, 12, 16, or 24bits) should occupy the most significant portion of TX (see Figure 6-48). The unused bits(least significant portion) of TX are don’t care bits. The DSP is interrupted whenever TXbecomes empty if the transmit data register empty interrupt has been enabled.6.4.2.3.13Time Slot Register (TSR)TSR is effectively a null data register that is used when the data is not to be transmittedin the available transmit time slot. For the purposes of timing, TSR is a write-only registerthat behaves like an alternative transmit data register, except that, rather than transmittingdata, the transmit data pin is in the high-impedance state for that time slot.6.4.3Operational Modes and Pin DefinitionsTable 6-12 and Table 6-13 completely describe the SSI operational modes and pin definitions(Table 6-5 is a simplified version of these tables).
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