Сигнальный МП Motorola DSP56002 (1086189), страница 53
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Read RX and ignore the dataFreescale Semiconductor, Inc...3. Do nothing – the receiver overrun exception will occur at the end of the currenttime slot4. Toggle RE to disable the receiver until the next frame, and read RX to clear RDFFigure 6-79 is essentially the same program shown in Figure 6-74 except that this program uses the network mode to receive only right-channel data. In the “Initialize SSI Port”section of the program, two words per frame are selected using the DC bits in the CRA,and the network mode is selected by setting MOD to one in the CRB. If the program inFigure 6-78 is used to transmit to the program in Figure 6-79, the correct data will appearin the data buffer for the right channel, but the buffer for the left channel will probably contain $000000 or $FFFFFF, depending on whether the transmitter output was high or lowwhen TSR was written and whether the output was three-stated.6.4.7.4On-Demand Mode ExamplesA divide ratio of one (DC=00000) in the network mode is defined as the on-demand modeof the SSI because it is the only data-driven mode of the SSI – i.e., data is transferredwhenever data is present (see Figure 6-80 and Figure 6-81).
STD and SCK from DSP1are connected to DSP2 – SRD and SC0, respectively. SC0 is used as an input clock pinin this application. Receive data and receive data clock are separate from the transmit signals. On-demand data transfers are nonperiodic, and no time slots are defined. Whenthere is a clock in the gated clock mode, data is transferred. Although they are not necessarily needed, frame sync and flags are generated when data is transferred.
Transmitterunderruns (TUE) are impossible in this mode and are therefore disabled. In the on-demand transmit mode, two additional SSI clock cycles are automatically inserted betweeneach data word transmitted. This procedure guarantees that frame sync will be low between every transmitted data word or that the clock will not be continuous between twoconsecutive words in the gated clock mode. The on-demand mode is similar to the SCIshift register mode with SSFTD equals one and SCKP equals one. The receiver shouldbe configured to receive the bit clock and, if continuous clock is used, to receive an external frame sync.
Therefore, for all full-duplex communication in on-demand mode, theasynchronous mode should be used. The on-demand mode is SPI compatible.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 145Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...DSP56002DSP1DSP56002DSP2STDSRDSCKSCOSRDSTDSC0SCKFigure 6-80 On Demand ExampleInitializing the on-demand mode for the example illustrated in Figure 6-81 is accomplishedby setting the bits in CRA and CRB as follows:1.The word length must be selected by setting WL1 and WL0.
In this example, a24-bit word length was chosen (WL1=1 and WL0=1).2.The on-demand mode is selected by clearing DC4–DC0.3.The serial clock rate must be selected by setting PSR and PM7–PM0 (seeTable 6-15 (a), Table 6-15 (b), and Table 6-16).4.RE and TE must be set to activate the transmitter and receiver. If interruptsare to be used, RIE and TIE should be set.
RIE and TIE are usually set aftereverything else is configured and the DSP is ready to receive interrupts.5.The network mode must be selected (MOD=1).6.A gated clock (GCK=1) is selected in this example. A continuous clock example is shown in Figure 6-78.7.Asynchronous clock control was selected (SYN=0) in this example.8.Since gated clock is used, the frame sync is not necessary. FSL1 and FSL0can be ignored.9.SCKD must be an output (SCKD=1).10.SCD0 must be an input (SCD0=0).11.Control bit SHFD should be set as needed for the application. Pins SC1 andSC2 are undefined in this mode (see Table 6-13) and should be programmedas general-purpose I/O pins.6 - 146PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)SSI CONTROL REGISTER A (CRA)(READ/WRITE)1514X:$FFEC PSR1WL113121WL01100DC4DC324-BIT WORD LENGTH100DC29087654320PM7PM6PM5PM4PM3PM2PM1PM0DC1DC010ON-DEMANDFreescale Semiconductor, Inc...SSI CONTROL REGISTER B (CRB)(READ/WRITE)X:$FFED15141312RIETIERETE11109876543210110FSL1FSL0SHFD1SCD2SCD10OF1OF0SCD0SERIAL CONTROL 2DIRECTION0 = INPUTMODSSI MODE SELECT1 = NETWORKGCKGATED CLOCK CONTROL1=GATED CL0CKSCKDCLOCK SOURCEDIRECTION1 = OUTPUTSYNSYNC/ASYNC CONTROL0 = ASYNCHRONOUSTRANSMIT CLOCK24-BIT DATA FROM DSP1 TO DSP2TRANSMIT DATARECEIVE CLOCKTWO SSI BIT CLOCKS (MIN.)RECEIVE DATADSP2 TO DSP124-BIT DATA FROM DSP2 TO DSP1NOTE: Two SSI bit clock times are automatically inserted between each data word.
This guarantees frame syncwill be low between every data word transmitted and the clock will not be continuous for two consecutivedata words.Figure 6-81 On-Demand Data-Driven Network ModeMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 147Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)DATA CHANGESSERIAL CLOCKDATA STABLEFRAME SYNCSERIAL DATAFreescale Semiconductor, Inc...DATADATA(a) ContinuousSERIAL CLOCKSERIAL DATADATADATA(b) GatedFigure 6-82 Clock Modes6.4.7.4.1On-Demand Mode – Continuous ClockThis special case will not generate a periodic frame sync.
A frame sync pulse will be generated only when data is available to transmit (see Figure 6-82(a)). The frame sync signalindicates the first time slot in the frame. The on-demand mode requires that the transmitframe sync be internal (output) and the receive frame sync be external (input). Therefore,for simplex operation, the synchronous mode could be used; however, for full-duplex operation, the asynchronous mode must be used. Data transmission that is data driven isenabled by writing data into TX. Although the SSI is double buffered, only one word canbe written to TX, even if the transmit shift register is empty.
The receive and transmit interrupts function as usual using TDE and RDF; however, transmit and receive underrunsare impossible for on-demand transmission and are disabled. This mode is useful for interfacing to codecs requiring a continuous clock.6.4.7.4.2On-Demand Mode – Gated ClockGated clock mode (see Figure 6-82(b)) is defined for on-demand mode, but the gatedclock mode is considered a frame sync source; therefore, in gated clock mode, the transmit clock must be internal (output) and the receive clock must be external (input). For ondemand mode, with internal (output) synchronous gated clock, output clock is enabled for6 - 148PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)the transmitter and receiver when TX data is transferred to the transmit data shift register.This SPI master operating mode is shown in Figure 6-83.
Word sync is inherent in theclock signal, and the operation format must provide frame synchronization.Freescale Semiconductor, Inc...Figure 6-84 is the block diagram for the program presented in Figure 6-85. This programcontains a transmit test program that was written as a scoping loop (providing a repetitivesync) using the on-demand, gated, synchronous mode with no interrupts (polling) to transmit data to the program shown in Figure 6-86. The program also demonstrates usingGPIO pins as general-purpose control lines.
PC3 is used as an external strobe or enablefor hardware such as an A/D converter.The transmit program sets equates for convenience and readability. Test data is then written to X: memory, and the data pointer is initialized. Setting M0 to two makes the buffercircular (modulo 3), which saves the step of resetting the pointer each loop. PC3 is configured as a general-purpose output for use as a scope sync, and CRA and CRB are theninitialized. Setting the PCC bits begins SSI operation; however, no data will be transmitteduntil data is written to TX. PC3 is set high at the beginning of data transmission; data isthen moved to TX to begin transmission.
A JCLR instruction is then used to form a waitloop until TDE equals one and the SSI is ready for another data word to be transmitted.Two more data words are transmitted in this fashion (this is an arbitrary number chosenfor this test loop). An additional wait is included to make sure that the frame sync has gonelow before PC3 is cleared, indicating on the scope that transmission is complete. A waitof 100 NOPs is implemented by using the REP instruction before starting the loop again.MASTERSLAVESHIFT REGISTERSHIFT REGISTERDSP1DSP2SPICLOCK GENERATORFigure 6-83 SPI ConfigurationMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 149Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)DSP56002DSP56002PC3SC2SRDSTDSCKFreescale Semiconductor, Inc...SCK15KFigure 6-84 On-Demand Mode Example — Hardware Configuration;*************************************************;SSI and other I/O EQUATES*;*************************************************CRAEQU$FFECCRBEQU$FFEDPCCEQU$FFE1PCDEQU$FFE5SSISREQU$FFEETXEQU$FFEFPCDDR EQU$FFE3ORGDCDCDCX:0$AA0000$330000$F00000;Data to transmit.;*************************************************;MAIN PROGRAM*;*************************************************ORGP:$40MOVEMOVE#0,R0#2,M0;Pointer to data buffer;Length off buffer is 3Figure 6-85 On-Demand Mode Transmit Example Program (Sheet 1 of 2)6 - 150PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOVEP #$08,X:PCDDR;SC0 (PC3) as general purpose output.MOVEP #$001F,X:CRAMOVEP #$1E30,X:CRB;Set Word Length=8, CLK=5.12/32 MHz.;Enable transmitter, Mode=On- Demand,;Gated clock on, synchronous mode,;Word frame sync selected, frame;sync and clock are internal and;output to port pins.;Set PCC for SSI andMOVEP #$1F0,X:PCCFreescale Semiconductor, Inc...LOOP0BSET#3,X:PCDTDE3;Set PC3 high (this is example enable;or strobe for an external device:such as an ADC).MOVEP X:(R0);pl,X:TX;Move data to TX registerJCLR#6,X:SSISR,TDE1 ;Wait for TDE (transmit data register;empty) to go high.MOVEP X:(R0);pl,X:TX;Move next data to TX.JCLR#6,X:SSISR,TDE2 ;Wait for TDE to go high.MOVEP X:(R0);pl,X:TX;Move data to TX.JCLR#6,X:SSISR,TDE3 ;Wait for TDE=1.FSCJSET#5,X:PCD,FSC;Wait for frame sync to go low.
NOTE:;State of frame sync is directly;determined by reading PC5.BCLR#3,X:PCD;Set PC3 lo (example external enable).TDE1TDE2;anything goes here (i.e., any processing)REP#100NOPJMPLOOP0;Continue sequence forever.ENDFigure 6-85 On-Demand Mode Transmit Example Program (Sheet 2 of 2)Figure 6-86 is the receive program for the scoping loop program presented in Figure 6-85.The receive program also uses the on-demand, gated, synchronous mode with no interrupts (polling).
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