Сигнальный МП Motorola DSP56002 (1086189), страница 54
Текст из файла (страница 54)
Initialization for the receiver is slightly different than for the transmitter. InCRB, RE is set rather than TE, and SCKD and SCD2 are inputs rather than outputs. Afterinitialization, a JCLR instruction is used to wait for a data word to be received (RDF=1).MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 151Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)When a word is received, it is put into the circular buffer and loops to wait for another dataword. The data in the circular buffer will be overwritten after three words are received(does not matter in this application).Freescale Semiconductor, Inc...;*************************************************;SSI and other I/O EQUATES*;*************************************************CRAEQU$FFECCRBEQU$FFEDPCCEQU$FFE1PCDEQU$FFE5SSISREQU$FFEERXEQU$FFEFPCDDR EQU$FFE3;*************************************************;MAIN PROGRAM*;*************************************************ORGP:$40MOVEMOVE#0,R0#2,M0MOVEP #$001F,X:CRAMOVEP #$1E30,X:CRBMOVEP #$1F0,X:PCC;Pointer to data buffer;Length of buffer is 3;Set Word Length=8, CLK=5.12/32 MHz.;Enable receiver, Mode=On-Demand,;gated clock on, synchronous mode,;Word frame sync selected, frame;sync and clock are external.;Set PCC for SSILOOPRDF1JCLR#7,X:SSISR,RDF1 ;Wait for RDF (receive data register;Full) go to high.MOVEP X:RX,X:(R0)+;Read data from RX into memory.JMPLOOP;Continue sequence forever.ENDFigure 6-86 On-Demand Mode Receive Example Program6 - 152PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.8FlagsTwo SSI pins (SC1 and SC0) are available in the synchronous mode for use as serial I/Oflags.
The control bits (OF1 and OF0) and status bits (IF1 and IF0) are double bufferedto/from SC1 and SC0. Double buffering the flags keeps them in sync with TX and RX. Thedirection of SC1 and SC0 is controlled by SCD1 and SCD0 in CRB.Figure 6-87 shows the flag timing for a network mode example. Initially, neither TIE norTE is set, and the flag outputs are the last flag output value. When TIE is set, a TDE interrupt occurs (the transmitter does not have to be enabled for this interrupt to occur).Data (D1) is written to TX, which clears TDE, and the transmitter is enabled by software.When the frame sync occurs, data (D1) is transferred to the transmit shift register, settingTDE.
Data (D1) is shifted out during the first word time, and the output flags are updated.These flags will remain stable until the next frame sync. The TDE interrupt is then servicedby writing data (D2) to TX, clearing TDE. After the TSR completes transmission, the transmit pin is three-stated until the next frame syncFigure 6-88 shows a speaker phone example that uses a DSP56002 and two codecs. Noadditional logic is required to connect the codecs to the DSP.
The two serial output flagsin this example (OF1 and OF0) are used as chip selects to enable the appropriate codecfor I/O. This procedure allows the transmit lines to be ORed together. The appropriate output flag pin changes at the same time as the first bit of the transmit word and remains stable until the next transmit word (see Figure 6-89). Applications include serial-device chipselects, implementing multidrop protocols, generating Bell PCM signaling frame syncs,and outputting status information.Initializing the flags (see Figure 6-89) is accomplished by setting SYN, SCD1, and SCD0.No other control bits affect the flags.
The synchronous control bit must be set (SYN=1) toselect the SC1 and SC0 pins as flags. SCD1 and SCD0 select whether SC1 and SC0 areinputs or outputs (input=0, output=1). The other bits selected in Figure 6-89 are chosenfor the speaker phone example in Figure 6-88. In this example, the codecs require thatthe SSI be set for normal mode (MOD=0) with a gated clock (GCK=1) out (SCKD=1).Serial input flags, IF1 and IF0, are latched at the same time as the first bit is sampled inthe receive data word (see Figure 6-90). Since the input was latched, the signal on theinput flag pin can change without affecting the input flag until the first bit of the next receivedata word.
To initialize SC1 or SC0 as input flags, the synchronous control bit in CRBmust be set to one (SYN=1) and SCD1 set to zero for pin SC1, and SCD0 must be set tozero for pin SC0. The input flags are bits 1 and 0 in the SSISR (at X:$FFEE).MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 1536 - 154For More Information On This Product,Go to: www.freescale.comPORT C*D1D1D1D2F1WORDTIMETIME SLOTFigure 6-87 Output Flag TimingNOTES:1.
Fn = flags associated with Dn data.2. Output flags are double buffered with transmit data.3. Output flags change when data is transferred from TX to the transmit data shift register.4. Initial flag outputs (*) = last flag output value.5. Data and flags transition after external frame sync but not before rising edge of clock.OUTPUT FLAGSDATA WORDLOAD TSRTDE INTERRUPTSTETIEFRAME SYNCSTARTD2D2D3F2Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MC15500CODEC FILTER 1SPEAKER PHONETDDMICROPHONETXIRDDTDCRDCSPEAKERRXOOF0RCEOUTPUTFLAG 0MSIFreescale Semiconductor, Inc...DSP5002TDESRDSTDSCKSC0MC15500CODEC FILTER 2SC1TDDPHONE LINE INPUTTXIRDDTDCRDCPHONE LINE OUTPUTRXOOF1TDERCEOUTPUTFLAG 1MSINOTE: SC0 and SC1 are output flag 0 and 1 used to software select either filter 1 or 2.Figure 6-88 Output Flag ExampleMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 1556 - 156TIERIERE13For More Information On This Product,Go to: www.freescale.comPORT CB6B5B4110B319B2B1FSL07B0SHFD615SCD2413OUTPUT FLAGS ARE ALWAYS VALID UNTILTHE NEXT WORD TRANSMITTED.FSL18Figure 6-89 Output Flag Initialization011VALID OUTPUT FLAGB7TE12OF0 AND LF1 ARE CLOCKED OUT ON THERISING EDGE OF THE TRANSMIT CLOCK.OUTPUT FLAGTRANSMIT DATATRANSMIT CLOCKSCD1 AND SCD0SERIAL CONTROL 1 AND 0 DIRECTION1 = OUTPUTSCKDCLOCK SOURCE DIRECTION1 = OUTPUTSYNSYNC/ASYNC CONTROL1 = SYNCHRONOUSGCKGATED CLOCK CONTROL1 = GATED CLOCKMODSSI MODE SELECT0 = NORMAL1415Freescale Semiconductor, Inc...121 = FILTER 10 = FILTER 21OF000OF11Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)X:$FFEE76543210RDFTDEROETUERFSTFSIF1IF0SSI STATUS REGISTER (SSISR)(READ)INPUT FLAGSRECEIVE CLOCKRECEIVE DATAB7B6B5B4B3B2B1B0Freescale Semiconductor, Inc...INPUT FLAGSAMPLEFigure 6-90 Input Flags6.4.9Example CircuitsThe DSP-to-DSP serial network shown in Figure 6-91 uses no additional logic chips for thenetwork connection.
All serial data is synchronized to the data source (all serial clocks andserial syncs are common). This basic configuration is useful for decimation and data reduction when more processing power is needed than one DSP can provide. Cascading DSPsin this manner is useful in several network topologies including star and ring networks.DSP56002DSP56002DSP56002DSP56002DATAINDATAOUTSRDSTDSRDSTDSRDSTDSRDSTDSCKSCKSCKSCKSC2SC2SC2SC2SERIAL CLOCKSERIAL SYNCFigure 6-91 SSI Cascaded Multi-DSP SystemMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 157Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...SYNCHRONOUS SERIAL INTERFACE (SSI)TDM networks are useful to reduce the wiring needed for connecting multiple processors.A TDM parallel topology, such as the one shown in Figure 6-92, is useful for interpolatingfilters.
Serial data can be received simultaneously by all DSPs, processing can occur inparallel, and the results are then multiplexed to a single serial data out line. This configuration can be cascaded and/or looped back on itself as needed to fit a particular application (see Figure 6-93). The serial and parallel configurations can be combined to form thearray processor shown in Figure 6-94.
A nearest neighbor array, which is applicable tomatrix relaxation processing, is shown in Figure 6-95. To simplify the drawing, only thecenter DSP is connected in this illustration. In use, all DSPs would have four three-statebuffers connected to their STD pin. The flags (SC0 and SC1) on the control master operate the three-state buffers, which control the direction that data is transferred in the matrix(north, south, east, or west).The bus architecture shown in Figure 6-96 allows data to be transferred between any twoDSPs.
However, the bus must be arbitrated by hardware or a software protocol to preventcollisions. The master/slave configuration shown in Figure 6-97 also allows data to betransferred between any two DSPs but simplifies network control.6 - 158PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)DSP56002SRDSTDSCKSC2Freescale Semiconductor, Inc...DSP56002SRDSTDSCKSERIALDATA INSERIALDATA OUTSC2DSP56002SRDSTDSCKSC2DSP56002SRDSTDSCKSC2SERIAL SYNCSERIAL CLOCKFigure 6-92 SSI TDM Parallel DSP NetworkMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 159Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)DSP56002Freescale Semiconductor, Inc...SRDDSP56002STDSRDSCKSCKSC2SC2DSP56002SRDDSP56002STDSRDSCKSC2SC2DSP56002STDSRDSTDSCKSCKSC2SC2DSP56002SRDSTDSCKDSP56002SRDSTDDSP56002STDSRDSTDSCKSCKSC2SC2SERIAL CLOCKFRAME SYNCFigure 6-93 SSI TDM Connected Parallel Processing Array6 - 160PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)DSP56002Freescale Semiconductor, Inc...SRDDSP56002STDSRDSTDSRDSTDSCKSCKSCKSC2SC2SC2DSP56002SRDDSP56002DSP56002STDSRDDSP56002STDSRDSTDSERIALINSERIALOUTSCKSCKSCKSC2SC2SC2DSP56002SRDDSP56002STDSRDSTDSRDSTDSCKSCKSCKSC2SC2SC2DSP56002SRDDSP56002DSP56002STDSRDDSP56002STDSRDSTDSCKSCKSCKSC2SC2SC2SERIAL CLOCKSERIAL SYNCFigure 6-94 SSI TDM Serial/Parallel Processing ArrayMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 161Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)DSP56002DSP56002SRDSRDSTDSC0SCKSCKSCKSC1SC2SC2SC2DSP56002Freescale Semiconductor, Inc...DSP56002SRDSRDDSP56002STDSRDSTDDSP56002STDSRDSTDSCKSCKSCKSC2SC2SC2DSP56002SRDSTDDSP56002STDSRDDSP56002STDSRDSTDSCKSCKSCKSC2SC2SC2SERIAL CLOCKFRAME SYNCFigure 6-95 SSI Parallel Processing — Nearest Neighbor Array6 - 162PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)SERIAL SYNCSERIAL CLOCKSERIAL DATA BUSFreescale Semiconductor, Inc...DSP56002DSP56002DSP56002DSP56002STDSTDSTDSTDSRDSRDSRDSRDSCKSCKSCKSCKSC2SC2SC2SC2Figure 6-96 SSI TDM Bus DSP NetworkMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 1636 - 164For More Information On This Product,Go to: www.freescale.comPORT CSRDSCKSC2SC1SC0SRDSCKSC2SC1SC0SC0SC1SC2SCKSRDSTDDSP56002SLAVE 2Figure 6-97 SSI TDM Master-Slave DSP NetworkNOTE: Flags can specify data types: control, address, and data.FLAG 0FLAG 1MASTER SYNCMASTER CLOCKSTDDSP56002SLAVE 1STDDSP56002MASTERMASTER RECEIVEMASTER TRANSMITFreescale Semiconductor, Inc...SC0SC1SC2SCKSRDSTDDSP56002SLAVE 3Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SECTION 7Freescale Semiconductor, Inc...DSP56002 TIMER ANDEVENT COUNTERMOTOROLAFor More Information On This Product,Go to: www.freescale.com7-1Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...SECTION CONTENTS7.1INTRODUCTION .
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
