Сигнальный МП Motorola DSP56002 (1086189), страница 58
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3Freescale Semiconductor, Inc...A.1A-2BOOTSTRAP AND ROM CODEFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.INTRODUCTIONA.1INTRODUCTIONFreescale Semiconductor, Inc...This section presents the Bootstrap program contained in the DSP56002 64-word BootROM.
This program can load the internal program RAM starting at P:$0 from an externalEPROM or the Host Interface, and may load any program RAM segment from the SCIserial interface.If MC:MB:MA=001, the program loads the internal program RAM from 1,536 consecutivebyte-wide P memory locations, starting at P:$C000 (bits 7-0).
These will be packed into512 24-bit words and stored in contiguous program RAM memory locations starting atP:$0. After assembling one 24-bit word, the bootstrap program stores the result in internal program RAM memory. Note that the routine loads data starting with the least significant byte of P:$0.If MC:MB:MA=10x, the program loads internal program RAM from the Host Interface, starting at P:$0. If only a portion of the P memory is to be loaded, the Host Interface bootstrapload program may be stopped by setting Host Flag 0 (HF0). This will terminate the bootstrap loading operation and start executing the loaded program at location P:$0 of theinternal program RAM.If MC:MB:MA=11x, the program loads program RAM from the SCI interface.
The numberof program words to be loaded and the starting address must be specified. The SCI bootstrap code expects to receive 3 bytes specifying the number of program words, 3 bytesspecifying the address in internal program RAM to start loading the program words andthen 3 bytes for each program word to be loaded. The number of words, the startingaddress and the program words are received least significant byte first followed by themid and then by the most significant byte.
After receiving the program words, programexecution starts at the same address where loading started. The SCI is programmed towork in asynchronous mode with 8 data bits, 1 stop bit and no parity. The clock source isexternal and the clock frequency must be 16x the baud rate. After each byte is received,it is echoed back through the SCI transmitter.The bootstrap program listing is shown in Figure A-1.MOTOROLABOOTSTRAP AND ROM CODEFor More Information On This Product,Go to: www.freescale.comA-3Freescale Semiconductor, Inc.INTRODUCTIONFreescale Semiconductor, Inc...; BOOTSTRAP CODE FOR DSP56002 - (C) Copyright 1990 Motorola Inc.; Revised October 24, 1990.;; Bootstrap through the Host Interface, External EPROM or SCI.;;BOOTEQU$C000; this is the location in P memory; on the external memory bus; where the external byte-wide; EPROM would be locatedPBCHSRHRXPCCSCRSSRSCCRSRXLSTXLSTARTEQUEQUEQUEQUEQUEQUEQUEQUEQU$FFE0$FFE9$FFEB$FFE1$FFF0$FFF1$FFF2$FFF4$FFF4; Port B Control Register; Host Status Register; Host Receive Register; Port C Control Register; SCI Control Register; SCI Status Register; SCI Clock Control Register; SCI Receive Register Low; SCI Transmit Register LowORGPL:$0,PL:$0; bootstrap code starts at $0MOVE#<0,R0JCLRJSET#4,OMR,EPROMLD#1,OMR,SCILD; default P address where prog; will begin loading; If MC:MB:MA=0xx, go load from EPROM; If MC:MB:MA=11x, go load from SCI; This routine loads from the Host Interface.; MC:MB:MA=100 - reserved; MC:MB:MA=101 - HostHOSTLD_LBLA_LBLBBSETDOJCLRENDDOJMP#0,X:PBC#512,_LOOP3#3,X:HSR,_LBLBJCLR#0,X:HSR,_LBLA<_LOOP3MOVEP X:HRX,P:(R0)+_LOOP3JMP; Configure Port B as Host; Load 512 instruction words; if HF0=1, stop loading data.; Must terminate the do loop<FINISH; Wait for HRDF to go high; (meaning data is present).; Store 24-bit data in P mem.; and go get another 24-bit word.; finish bootstrapFigure A-1 DSP56002 Bootstrap Program (Sheet 1 of 3)A-4BOOTSTRAP AND ROM CODEFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.INTRODUCTION; This routine loads from external EPROM.; MC:MB:MA=001EPROMLDMOVEDODOMOVEMREPASR#BOOT,R1#512,_LOOP1#3,_LOOP2P:(R1)+,A2#8A_LOOP2Freescale Semiconductor, Inc..._LOOP1FINISHMOVEM A1,P:(R0)+; and go get another 24-bit word.MOVE#<0,R1JMP<BOOTEND; R1 = Ext address of EPROM; Load 512 instruction words; Each instruction has 3 bytes; Get the 8 LSB from ext.
P mem.; Shift 8 bit data into A1; Get another byte.; Store 24-bit result in P mem.; finish bootstrap; This routine loads from the SCI.; MC:MB:MA=110 - external SCI clock; MC:MB:MA=111 - reservedSCILDMOVEPJMPNOP#$0302,X:SCR<EXTC; Configure SCI Control Reg; go to next boot rom segment; just to fill the last spaceORGPL:$100,PL:$100; starting address of 2nd 32-word bootstrap ROMEXTCMOVEPMOVEP#$C000,X:SCCR#7,X:PCC; Configure SCI Clock Control Reg; Configure SCLK, TXD and RXD_SCI1DO#6,_LOOP6JCLRMOVEPJCLRMOVEPREPASR#2,X:SSR,*X:SRXL,A2#1,X:SSR,*A2,X:STXL#8A; get 3 bytes for number of; program words and 3 bytes; for the starting address; Wait for RDRF to go high; Put 8 bits in A2; Wait for TDRE to go high; echo the received byteMOVEMOVEDOA1,R0A1,R1A0,_LOOP4DOJCLRMOVEPJCLRMOVEPREPASR#3,_LOOP5#2,X:SSR,*X:SRXL,A2#1,X:SSR,*A2,X:STXL#8AMOVEMA1,P:(R0)+_LOOP6; starting address for load; save starting address; Receive program words; Wait for RDRF to go high; Put 8 bits in A2; Wait for TDRE to go high; echo the received byte_LOOP5; Store 24-bit result in P mem._LOOP4Figure A-1 DSP56002 Bootstrap Program (Sheet 2 of 3)MOTOROLABOOTSTRAP AND ROM CODEFor More Information On This Product,Go to: www.freescale.comA-5Freescale Semiconductor, Inc.INTRODUCTION; This is the exit handler that returns execution to normal; expanded mode and jumps to the RESET vector.BOOTENDANDI#$EC,OMRANDI#$0,CCRJMP(R1); Set operating mode to 0; (and trigger an exit from; bootstrap mode).; Clear CCR as if RESET to 0.; Delay needed for Op.
Mode change; Then go to starting Prog addr.Freescale Semiconductor, Inc...; End of bootstrap code. Number of program words: 64Figure A-1 DSP56002 Bootstrap Program (Sheet 3 of 3)A-6BOOTSTRAP AND ROM CODEFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.APPENDIX BFreescale Semiconductor, Inc...PROGRAMMING SHEETSThe following pages are a set of programming sheets intended to simplify programming the variousDSP56002 programmable registers.
The registers are grouped between the central processing moduleand each peripheral. Each register includes the name, address, reset value, and meaning of each bit. Thesheets provide room to write the value for each bit and the hexadecimal equivalent for each register.MOTOROLAFor More Information On This Product,Go to: www.freescale.comB-1Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...SECTION CONTENTSB.1PERIPHERAL ADDRESSES . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3B.2INTERRUPT VECTOR ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4B.3INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . B-5B.4CENTRAL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10B.5GP I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14B.6HOST . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16B.7SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21B.8SSI . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24B.9TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27B-2For More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.PERIPHERAL ADDRESSESFreescale Semiconductor, Inc...2316 15870X:$FFFFINTERRUPT PRIORITY REGISTER (IPR)X:$FFFEPORT A — BUS CONTROL REGISTER (BCR)X:$FFFDPLL CONTROL REGISTERX:$FFFCOnCE GDB REGISTERX:$FFFBRESERVEDX:$FFFARESERVEDX:$FFF9RESERVEDX:$FFF8RESERVEDX:$FFF7RESERVEDX:$FFF6SCI HI - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF5SCI MID - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF4SCI LOW - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF3SCI TRANSMIT DATA ADDRESS REGISTER (STXA)X:$FFF2SCI CONTROL REGISTER (SCCR)X:$FFF1SCI INTERFACE STATUS REGISTER (SSR)X:$FFF0SCI INTERFACE CONTROL REGISTER (SCR)X:$FFEFSSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX)X:$FFEESSI STATUS/TIME SLOT REGISTER (SSISR/TSR)X:$FFEDSSI CONTROL REGISTER B (CRB)X:$FFECSSI CONTROL REGISTER A (CRA)X:$FFEBHOST RECEIVE/TRANSMIT REGISTER (HRX/HTX)X:$FFEARESERVEDX:$FFE9HOST STATUS REGISTER (HSR)X:$FFE8HOST CONTROL REGISTER (HCR)X:$FFE7RESERVEDX:$FFE6RESERVEDX:$FFE5PORT C — DATA REGISTER (PCD)X:$FFE4PORT B — DATA REGISTER (PBD)X:$FFE3PORT C — DATA DIRECTION REGISTER (PCDDR)X:$FFE2PORT B — DATA DIRECTION REGISTER (PBDDR)X:$FFE1PORT C — CONTROL REGISTER (PCC)X:$FFE0PORT B — CONTROL REGISTER (PBC)X:$FFDFTIMER COUNT REGISTER (TCR)X:$FFDETIMER CONTROL/STATUS REGISTER (TCSR)= Read as random number; write as don’t care.X:$FFC0RESERVEDFigure B-1 On-chip Peripheral Memory MapMOTOROLAFor More Information On This Product,Go to: www.freescale.comB-3Freescale Semiconductor, Inc.INTERRUPT VECTOR ADDRESSESTable B-1Interrupts Starting Addresses and SourcesInterruptStartingAddress IPL Interrupt SourceFreescale Semiconductor, Inc...$0000$0002$0004$0006$0008$000A$000C$000E$0010$0012$0014$0016$0018$001A$001C$001E$0020$0022$0024$002633330-20-20-20-20-20-20-20-20-20-20-230-20-20-20-2•••$003A$003C$003E$0040•••$007EB-4Hardware RESETStack ErrorTraceSWIIRQAIRQBSSI Receive DataSSI Receive Data with Exception StatusSSI Transmit DataSSI Transmit Data with Exception StatusSCI Receive DataSCI Receive Data with Exception StatusSCI Transmit DataSCI Idle LineSCI TimerNMIHost Receive DataHost Transmit DataHost Command (default)Available for Host Command•••0-20-230-2Available for Host CommandTimerIllegal InstructionAvailable for Host Command•••0-2 Available for Host CommandFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.INSTRUCTIONSTable B-2Freescale Semiconductor, Inc...Mnemonic SyntaxABSADCADDADDLADDRANDAND(I)ASLASRBCHGBCLRBSETBTSTCLRCMPCMPMDEBUGDEBUGccDECDIVMOTOROLAParallel MovesDS,DS,DS,DS,DS,D#xx,DDD#n,X:<aa>#n,X:<pp>#n,X:<ea>#n,Y:<aa>#n,Y:<pp>#n,Y:<ea>#n,D#n,X:<aa>#n,X:<pp>#n,X:<ea>#n,Y:<aa>#n,Y:<pp>#n,Y:<ea>#n,D#n,X:<aa>#n,X:<pp>#n,X:<ea>#n,Y:<aa>#n,Y:<pp>#n,Y:<ea>#n,D#n,X:<aa>#n,X:<pp>#n,X:<ea>#n,Y:<aa>#n,Y:<pp>#n,Y:<ea>#n,DDS1,S2S1,S2DS,DInstruction Set Summary — Sheet 1 of 5Instruction Osc.Program ClockWords CyclesS LE UNZVC(parallel move) .
. . . . . .1+mv(parallel move) . . . . . . .1+mv(parallel move) . . . . . . .1+mv(parallel move) . . . . . . .1+mv(parallel move) . . . . . . .1+mv(parallel move) . . . . . . .1+mv.................... 1(parallel move) . . . . . . .1+mv(parallel move) .
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