Сигнальный МП Motorola DSP56002 (1086189), страница 38
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The SCI is then configured and the interrupts are unmasked, which starts the data transfer. The jump-to-self instruction (LAB0 JMP LAB0) isused to wait while interrupts transfer the data.6.3.7Asynchronous DataAsynchronous data uses a data format with embedded word sync, which allows an unsynchronized data clock to be synchronized with the word if the clock rate and number ofbits per word is known. Thus, the clock can be generated by the receiver rather than requiring a separate clock signal. The transmitter and receiver both use an internal clockthat is 16 × the data rate to allow the SCI to synchronize the data. The data format requires that each data byte have an additional start bit and stop bit.
In addition, two of theword formats have a parity bit. The multidrop mode used when SCIs are on a common6 - 44PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.Freescale Semiconductor, Inc...SERIAL COMMUNICATION INTERFACE (SCI)ORGJMPP:0$40ORGMOVEPNOPP:$14;SCI receive data vectorX:$FFF4,Y:(R0)+ ;Receive low byte of data;Fast interrupt responseMOVEPMOVEPX:$FFF1,X0;Receive with exception. Read status registerX:$FFF4,Y:(R0)+ ;Receive low byte of dataORGMOVEPMOVEMOVEMOVEPMOVEPMOVEPMOVEPMOVECLAB0 JMP;Reset vector;P:$40#0,X:$FFFE#$100,R0#$FF,M0#$C000,X:$FFFF#$900,X:$FFF0#$C000,X:$FFF2#7,X:$FFE1#0,SRLAB0;Clear BCR;Data ROM start address; Size of data ROM – wraps around at $200;Interrupt priority register; 8-bit synchronous mode receive only;Clock control register external clock;Port C control register – enable SCI;Unmask interrupts;Wait in loop for interruptsFigure 6-21 SCI Synchronous Receivebus has an additional data type bit.
The SCI can operate in full-duplex or half-duplexmodes since the transmitter and receiver are independent. The SCI transmitter and receiver can use either the internal clock (TCM=0 and/or RCM=0) or an external clock(TCM=1 and/or RCM=1) or a combination. If a combination is used, the transmitter andreceiver can run at different data rates.6.3.7.1Asynchronous Data ReceptionFigure 6-22 illustrates initializing the SCI data receiver for asynchronous data. The firststep (1) resets the SCI to prevent the SCI from transmitting or receiving data.
Step two (2)selects the desired operation by programming the SCR. As a minimum, the word format(WDS2, WDS1, and WDS0) must be selected, and (3) the receiver must be enabled(RE=1). If (4) interrupts are to be used, set RIE equals one. Use Table 6-3 (a) throughTable 6-4 (b) to set (5) the baud rate (SCP and CD0–CD11 in the SCCR). Once the SCIis completely configured, it is enabled by (6) setting the RXD bit in the PCC.The receiver is continually sampling RDX at the 16 × clock rate to find the idle-start-bittransition edge.
When that edge is detected (1) the following eight or nine bits, dependingon the mode, are clocked into the receive shift register (see Figure 6-23). Once a complete byte is received, (2) the character is latched into the SRX, and RDRF is set as wellMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 456 - 46For More Information On This Product,Go to: www.freescale.comPORT CTMIETIE12RIE111ILIE10RCMTCMSCP13COD12CD1111PRESCALERIF SCP = 1, THEN DIVIDE BY 8IF SCP = 0, THEN DIVIDE BY 11415CD1010CD99TE9NOTE:0Serial Interface197CC78CC8CD77WOMS7CC66CD66RWU6CC55CD55WAKE5CC44CD44SBK42CC33CD33RXDCC22CD22SSFTD WDS230CD00CC11SCIFigure 6-22 Asynchronous SCI Receiver Initialization10DIVIDE BY 1TO 4096CD11WDS1 WDS01If RE is cleared while a valid character is being received, the reception of the character will be completed before the receiver is disabled.GPIOFunction0CCx238RE18CD8SET THE RXD BIT IN PCC TO ENABLE THE SCI RECEIVER SYSTEM.X:$FFE16.STIRSCKP13SET THE BAUD RATE BY PROGRAMMING THE SCCR.X:$FFF25.1415HARDWARE OR SOFTWARE RESETPROGRAM SCR WITH DESIRED MODE AND FEATURES.TURN ON RECEIVER (RE = 1).OPTIONALLY ENABLE RECEIVER INTERRUPTS (RIE = 1).X:$FFF01.2.3.4.Freescale Semiconductor, Inc...PORT C CONTROL REGISTER (PCC)SCI CONTROL REGISTER (SCCR)(READ/WRITE)SCI CONTROL REGISTER (SCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)as the error flags, OR, PE, and FE.
If (3) interrupts are enabled, an interrupt is generated.MOTOROLAMOTOROLAFER8PE5OR4IDLE3For More Information On This Product,Go to: www.freescale.comPORT CSCI RECEIVE DATAINTERRUPTVECTORTABLEX:$FFF4X:$FFF55.23TRNE0X:$FFF6TDRE1SRX8 7READING SRX CLEARS RDRF IN THE SSR.SRX16 15STATUS REGISTER (SSR)(READ ONLY)THE RECEIVE INTERRUPT SERVICE ROUTINE READS THE RECEIVED CHARACTER.RDRF12Figure 6-23 SCI Character Reception4.RECEIVEINTERRUPTSERVICEROUTINEIF RIE = 1 IN SCR, THEN AN INTERRUPT IS GENERATED.X:$FFF167TRANSFERRING THE RECEIVED CHARACTER INTO SRX SETS RDRF IN THE SSR.RXDTHE RECEIVER IS IDLE UNTIL A CHARACTER IS RECEIVED IN THE DATA SHIFT REGISTER.P:$00143.2.1.Freescale Semiconductor, Inc...SRX0Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6 - 47Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...The interrupt service routine, which can be a fast interrupt or a long interrupt, (4) readsthe received character.
Reading the SRX (5) automatically clears RDFR in the SSR andmakes the SRX ready to receive another byte.If (1) an FE, PE, or OR occurs while receiving data (see Figure 6-24), (2) RDRF is set because a character has been received; FE, PE, or OR is set in the SSR to indicate that anerror was detected. Either (3) the SSR can be polled by software to look for errors, or (4)interrupts can be used to execute an interrupt service routine. This interrupt is differentfrom the normal receive interrupt and is caused only by receive errors. The long interruptservice routine should (5) read the SSR to determine what error was detected and then(6) read the SRX to clear RDRF and all three error flags.6.3.7.2Asynchronous Data TransmissionFigure 6-25 illustrates initializing the SCI data transmitter for asynchronous data.
The firststep (1) resets the SCI to prevent the SCI from transmitting or receiving data. Step two (2)selects the desired operation by programming the SCR. As a minimum, the word format(WDS2, WDS1, and WDS0) must be selected, and (3) the transmitter must be enabled(TE=1). If (4) interrupts are to be used, set TIE equals one. Use Table 6-3 (a) through Table 6-4 (b) to set (5) the baud rate (SCP and CD0–CD11 in the SCCR). Once the SCI iscompletely configured, it can be enabled by (6) setting the TXD bit in the PCC. Transmission begins with (7) a preamble of ones.If polling is used to transmit data (see Figure 6-26), the polling routine can look at eitherTDRE or TRNE to determine when to load another byte into STX.
If TDRE is used (1), onebyte may be loaded into STX. If TRNE is used (2), two bytes may be loaded into STX ifenough time is allowed for the first byte to begin transmission (see 6.3.2.4.2). If interruptsare used (3), then an interrupt is generated when STX is empty. The interrupt routine,which can be a fast interrupt or a long interrupt, writes (4) one byte into STX. If multidropmode is being used and this byte is an address, STXA should be used instead of STX.Writing STX or STXA (5) clears TDRE in the SSR. When the transmit data shift registeris empty (6), the byte in STX (or STXA) is latched into the transmit data shift register,TRNE is cleared, and TDRE is set.There is a provision to send a break or preamble. A break (space) consists of a period ofzeros with no start or stop bits that is as long or longer than a character frame.
A preamble(mark) is an inverted break. A preamble of 10 or 11 ones (depending on the word lengthselected by WDS2, WDS1, and WDS0) can be sent with the following procedure (see Figure 6-27). (1) Write the last byte to STX and (2) wait for TDRE equals one. This is the bytethat will be transmitted immediately before the preamble. (3) Clear TE and then again setit to one. Momentarily clearing TE causes the output to go high for one character frame.6 - 48PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAFor More Information On This Product,Go to: www.freescale.comPORT CR8PEOR4AT LEAST ONE BIT SETFE5IDLE3RDRF120X:$FFF15RIEPESCI RECEIVE DATAINTERRUPTVECTORTABLE6FE7R84OR32RDRF110TDRE TRNERECEIVE WITHEXCEPTIONINTERRUPTSERVICEROUTINESCI STATUS REGISTER (SSR)(READ ONLY)READ SRX. THIS CLEARS RDRF IN THE SSR AND CLEARS THE OR, PE, ANDFE FLAGS.SRX6.SRX8 7READ SSRSRX16 155.X:$FFF4X:$FFF5X:$FFF623Figure 6-24 SCI Character Reception with ExceptionINTERRUPT WITHEXCEPTIONIDLERXDSCI STATUS REGISTER (SSR)TDRE TRNE (READ ONLY)1IF RIE = 1 IN SCR, THEN AN INTERRUPT WITH ERROR IS GENERATED.P:$00164.X:$FFF16SSR CAN BE POLLED BY SOFTWARE.3.7THIS SETS RDRF AND SET OR, PE, OR FE IN SSR.XXXXXXXXSERIAL STRING OF BAD DATAA CHARACTER IS RECEIVED WITH AT LEAST ONE OF THE FOLLOWING ERRORS:— FRAMING ERROR (FE = BIT 6 IN SSR— PARITY ERROR (PE = BIT 5 IN SSR)— OVERRUN ERROR (OR = BIT 4 IN SSR)2.1.Freescale Semiconductor, Inc...0Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)If TE remains cleared for a longer period, the output will remain high for an even number6 - 496 - 50For More Information On This Product,Go to: www.freescale.comPORT CTMIETIE112RIE11ILIE10TE19RE8WOMS7Serial Interface1097CC78CC8CC66RWU6CC55WAKE5CC44SBK42CC3310TXDFigure 6-25 Asynchronous SCI Transmitter Initialization11SCICC00WDS1 WDS0If TE is cleared while transmitting a character, the transmission of the character will be completed before the transmitter is disabled.CC22SSFTD WDS23THE TRANSMITTER WILL FIRST BROADCAST A PREAMBLE OF ONES BEFORE BEGINNING DATA TRANSMISSION:10 ONES WILL BE TRANSMITTED FOR THE 10-BIT ASYNCHRONOUS MODE.11 ONES WILL BE TRANSMITTED FOR THE 11-BIT ASYNCHRONOUS MODE.GPIOFunction230CCxNOTE:7.STIRSCKP13SET THE SCI CLOCK PRESCALER BIT AND THE CLOCK DIVIDER BITS IN THE SCCR.SET THE TXD BIT IN PCC TO ENABLE THE SCI TRANSMITTER SYSTEM.X:$FFE15.6.1415HARDWARE OR SOFTWARE RESETPROGRAM SCR WITH DESIRED MODE AND FEATURES.TURN ON TRANSMITTER (TE = 1).OPTIONALLY ENABLE TRANSMITTER INTERRUPTS (TIE = 1).X:$FFF01.2.3.4.Freescale Semiconductor, Inc...PORT C CONTROL REGISTER (PCC)SCI CONTROL REGISTER (SCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAMOTOROLAFor More Information On This Product,Go to: www.freescale.comPORT C6.000130120110100908R87FE6PE5STORE ONECHARACTERINTO STX (A)THIS CLEARSTDRE IN SSR.4.5.TRANSMITINTERRUPTSERVICEROUTINEX:$FFF3X:$FFF4X:$FFF5X:$FFF623OR4STXIDLE316 15RDRF2TRNETDRESTX1011Figure 6-26 Asynchronous SCI Character TransmissionTHE CHARACTER IN STX IS COPIED INTO TRANSMIT DATA SHIFT REGISTER.TRNE IS CLEARED.TDRE IS SET.GO TO STEP 2.AVAILABLE FOR HOST COMMANDSCI TRANSMIT DATAINTERRUPT VECTOR TABLEWHEN STX IS EMPTY, THEN TDRE = 1.WHEN STX IS EMPTY AND THE TRANSMIT DATA SHIFT REGISTER IS EMPTY THEN TRNE = 1.IF TIE = 1 IN SCR AND TDRE = 1 IN SSR, THEN AN INTERRUPT IS GENERATED.P:$00181.2.3.X:$FFF11415Freescale Semiconductor, Inc...8 7STXASTXSCI STATUS REGISTER (SSR)(READ/WRITE)0TXDFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)of character frames until TE is set.
(4) Write the first byte to follow the preamble into SRX6 - 516 - 52ST•TMIETIE12RIE11TOGGLE (1 - 0 - 1) TO SEND ACHARACTER TIME OF ALLONES (MARKS)STIRSCKP13ILIE10TE9WOMS7RWU65WAKETOGGLE (0 - 1 - 0) TO SEND ACHARACTER TIME OF ALLZEROS (SPACES)RE8SBK4For More Information On This Product,Go to: www.freescale.comPORT CD1D3D4D5D6D51D6STARTOFBREAKD7 STOPSBK = 1D2CHARACTER ENDSBEFORE BREAK BEGINS.D4SBK = 0D0LAST CHARACTER1.2.3.4.0WDS1 WDS012D735679 10 129 10 12SBK = 1BREAK PERIOD IS AN EXACT MULTIPLE OFCHARACTER TIMES.8SBK = 1SPACES (ZEROS)IDLE LINE3ST412345FIRST CHARACTER67STOP STSCI INTERFACE CONTROL REGISTER (SCR)(READ/WRITE)5678SBK = 0STOPSTARTOFBREAK9 10D0D1FIRSTCHARACTERAFTER BREAKSTA STOP BIT AT THE END OF THE BREAK WILL BE INSERTEDBEFORE THE NEXT CHARACTER STARTS0Figure 6-27 Transmitting Marks and Spaces4STOPPREAMBLE OF 10 ONESWRITE THE LAST BYTE TO STX.WAIT FOR TRDE = 1. THE LAST BYTE IS NOW IN THE TRANSMIT SHIFT REGISTER.CLEAR TE AND SET BACK TO ONE.
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