Сигнальный МП Motorola DSP56002 (1086189), страница 33
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The parity and data type bits donot change position and remain adjacent to the stop bit. SSFTD is cleared by hardwareand software reset.6.3.2.1.3SCR Send Break (SBK) Bit 4A break is an all-zero word frame – a start bit zero, a character of all zeros (including anyparity), and a stop bit zero: i.e., 10 or 11 zeros depending on the WDS mode selected. IfSBK is set and then cleared, the transmitter completes transmission of any data, sends10 or 11 zeros, and reverts to idle or sending data.
If SBK remains set, the transmitter willcontinually send whole frames of zeros (10 or 11 bits with no stop bit). At the completionof the break code, the transmitter sends at least one high bit before transmitting any datato guarantee recognition of a valid start bit. Break can be used to signal an unusual condition, message, etc.
by forcing a frame error, which is caused by a missing stop bit.Hardware and software reset clear SBK.6.3.2.1.4SCR Wakeup Mode Select (WAKE) Bit 5When WAKE equals zero, an idle line wakeup is selected. In the idle line wakeup mode,the SCI receiver is re-enabled by an idle string of at least 10 or 11 (depending on WDSmode) consecutive ones.
The transmitter’s software must provide this idle string betweenconsecutive messages. The idle string cannot occur within a valid message because eachword frame contains a start bit that is a zero.When WAKE equals one, an address bit wakeup is selected. In the address bit wakeupmode, the SCI receiver is re-enabled when the last (eighth or ninth) data bit received in acharacter (frame) is one. The ninth data bit is the address bit (R8) in the 11-bit multidropmode; the eighth data bit is the address bit in the 10-bit asynchronous and 11-bit asynchronous with parity modes. Thus, the received character is an address that has to be processed by all sleeping processors – i.e., each processor has to compare the receivedcharacter with its own address and decide whether to receive or ignore all following characters.
WAKE is cleared by hardware and software reset.6.3.2.1.5SCR Receiver Wakeup Enable (RWU) Bit 6When RWU equals one and the SCI is in an asynchronous mode, the wakeup function isenabled – i.e., the SCI is put to sleep waiting for a reason (defined by the WAKE bit) towakeup. In the sleeping state, all receive flags, except IDLE, and interrupts are disabled.When the receiver wakes up, this bit is cleared by the wakeup hardware. The programmermay also clear the RWU bit to wake up the receiver.6 - 18PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)RWU can be used by the programmer to ignore messages that are for other devices on amultidrop serial network. Wakeup on idle line (WAKE=0) or wakeup on address bit(WAKE=1) must be chosen.1.
When WAKE equals zero and RWU equals one, the receiver will not respondto data on the data line until an idle line is detected.Freescale Semiconductor, Inc...2. When WAKE equals one and RWU equals one, the receiver will not respondto data on the data line until a data byte with bit 9 equal to one is detected.When the receiver wakes up, the RWU bit is cleared, and the first byte of data is received.If interrupts are enabled, the CPU will be interrupted, and the interrupt routine will read themessage header to determine if the message is intended for this DSP.1. If the message is for this DSP, the message will be received, and RWU willagain be set to one to wait for the next message.2.
If the message is not for this DSP, the DSP will immediately set RWU to one.Setting RWU to one causes the DSP to ignore the remainder of the messageand wait for the next message.RWU is cleared by hardware and software reset. RWU is a don’t care in the synchronous mode.6.3.2.1.6SCR Wired-OR Mode Select (WOMS) Bit 7When the WOMS bit is set, the SCI TXD driver is programmed to function as an opendrain output and may be wired together with other TXD pins in an appropriate bus configuration such as a master-slave multidrop configuration. An external pullup resistor is required on the bus. When the WOMS is cleared, the TXD pin uses an active internal pullup.This bit is cleared by hardware and software reset.6.3.2.1.7SCR Receiver Enable (RE) Bit 8When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, anddata transfer is inhibited to the receive data register (SRX) from the receive shift register.If RE is cleared while a character is being received, the reception of the character will becompleted before the receiver is disabled.
RE does not inhibit RDRF or receive interrupts.RE is cleared by a hardware and software reset.6.3.2.1.8SCR Transmitter Enable (TE) Bit 9When TE is set, the transmitter is enabled. When TE is cleared, the transmitter will complete transmission of data in the SCI transmit data shift register; then the serial output isMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 19Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)forced high (idle).
Data present in the SCI transmit data register (STX) will not be transmitted. STX may be written and TDRE will be cleared, but the data will not be transferredinto the shift register. TE does not inhibit TDRE or transmit interrupts. TE is cleared by ahardware and software reset.Freescale Semiconductor, Inc...Setting TE will cause the transmitter to send a preamble of 10 or 11 consecutive ones (depending on WDS). This procedure gives the programmer a convenient way to ensure thatthe line goes idle before starting a new message.
To force this separation of messagesby the minimum idle line time, the following sequence is recommended:1. Write the last byte of the first message to STX2. Wait for TDRE to go high, indicating the last byte has been transferred to thetransmit shift register3. Clear TE and set TE back to one. This queues an idle line preamble to immediately follow the transmission of the last character of the message (includingthe stop bit)4. Write the first byte of the second message to STXIn this sequence, if the first byte of the second message is not transferred to the STX priorto the finish of the preamble transmission, then the transmit data line will simply mark idleuntil STX is finally written.6.3.2.1.9SCR Idle Line Interrupt Enable (ILIE) Bit 10When ILIE is set, the SCI interrupt occurs when IDLE is set.
When ILIE is clear, the IDLEinterrupt is disabled. ILIE is cleared by hardware and software reset.An internal flag, the shift register idle interrupt (SRIINT) flag, is the interrupt request to theinterrupt controller. SRIINT is not directly accessible to the user.When a valid start bit has been received, an idle interrupt will be generated if both IDLE(SCI Status Register bit 3) and ILIE equals one. The idle interrupt acknowledge from theinterrupt controller clears this interrupt request. The idle interrupt will not be assertedagain until at least one character has been received. The result is as follows:1. The IDLE bit shows the real status of the receive line at all times.2. Idle interrupt is generated once for each idle state, no matter how long the idlestate lasts.6 - 20PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6.3.2.1.10SCR SCI Receive Interrupt Enable (RIE) Bit 11The RIE bit is used to enable the SCI receive data interrupt.
If RIE is cleared, receive interrupts are disabled, and the RDRF bit in the SCI status register must be polled to determine if the receive data register is full. If both RIE and RDRF are set, the SCI will requestan SCI receive data interrupt from the interrupt controller.One of two possible receive data interrupts will be requested:Freescale Semiconductor, Inc...1. Receive without exception will be requested if PE, FE, and OR are all clear(i.e., a normal received character).2. Receive with exception will be requested if PE, FE, and OR are not all clear(i.e., a received character with an error condition).RIE is cleared by hardware and software reset.6.3.2.1.11SCR SCI Transmit Interrupt Enable (TIE) Bit 12The TIE bit is used to enable the SCI transmit data interrupt.
If TIE is cleared, transmitdata interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCIstatus register must be polled to determine if the transmit data register is empty. If bothTIE and TDRE are set, the SCI will request an SCI transmit data interrupt from the interrupt controller. TIE is cleared by hardware and software reset.6.3.2.1.12SCR Timer Interrupt Enable (TMIE) Bit 13The TMIE bit is used to enable the SCI timer interrupt. If TMIE is set (enabled), the timerinterrupt requests will be made to the interrupt controller at the rate set by the SCI clockregister. The timer interrupt is automatically cleared by the timer interrupt acknowledgefrom the interrupt controller.
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