Сигнальный МП Motorola DSP56002 (1086189), страница 30
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ASSERT HREQ TO START DMA TRANSFER.0HM1INIT7017Figure 5-40 DSP to Host DMA ProcedureRXH01•••RXHRXM01$0X:$FFE86. DMA CONTROLLER PERFORMS READS.WRITE ICRDMA CONTROLLERFreescale Semiconductor, Inc...1HRIE1HTIE0TREQ RREQ00HOST CONTROLREGISTER (HCR)INTERRUPTCONTROLREGISTER (ICR)Freescale Semiconductor, Inc.HOST INTERFACE (HI)MOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.6.4Example CircuitsFigure 5-41, Figure 5-42, and Figure 5-43 illustrate the simplicity of the HI. TheMC68HC11 in Figure 5-42 has a multiplexed address and data bus which requires thatthe address be latched. Although the HACK is not used in this circuit, it is pulled up.
Allunused input pins should be terminated to prevent erroneous signals. When determiningwhether a pin is an input, keep in mind that it may change during reset or while changingPort B between general purpose I/O and HI functions.The MC68000 (see Figure 5-42) can use a MOVEP instruction with word and long-worddata size to transfer multiple bytes. If an MC68020 or MC68030 is used, dynamic bus sizing can be used to transfer multiple bytes with any instruction.Figure 5-43 is a high level block diagram of a system using a single host to control multipleDSPs.
In addition, the DSPs use the SSI to network together the DSPs and multiplecodecs. This system, as shown with four DSPs, can process 80 million instructions per+5 VMC68HC11+5 VIRQDSP56002HACK(HOST ACKNOWLEDGE)HREQ(HOST REQUEST)ADDRESSDECODEA8 - A15HENE(HOST ENABLE)HR/W(HOST READ/WRITE)R/WA3 - A7LEADDRESSLATCHASA0 - A2A0/D0 - A7/D7HA0 - HA2(HOST ADDRESS)H0 - H7(HOST DATA)Use LDA and STA for 8-Bit Transfers.Use LDD and STD for 16-Bit Transfers.Figure 5-41 MC68HC11 to DSP56002 Host InterfaceMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 63Freescale Semiconductor, Inc.HOST INTERFACE (HI)+5 VMC68000IPL0 - IPL2A4 - A23INTERRUPTENCODERDSP56002HREQADDRESSDECODEFC0 - FC2HENFreescale Semiconductor, Inc...LDSASINTERRUPTVECTORDECODEDTACKBERRHACKDTACKTIMINGGENERATORR/WHR/WA1 - A3HA0 - HA2D0 - D7H0 - H7MC68000 — USE MOVEP for multiple byte transfers.MC68020 or MC68030 — Any Memory references will work due to dynamic bus sizing.Figure 5-42 MC68000 to DSP56002 Host Interfacesecond at 40 MHz and can be easily expanded if more processing power is needed.5 - 64PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL DATAFRAME SYNCCLOCKFLAG 1FLAG 0DATA BUSADDRESS BUSRD/WRREQHOST INTERFACE (HI)RXHOSTSSIANALOGINPUTFreescale Semiconductor, Inc...SELECTCODECDSP56002ANALOGOUTPUTTXRXHOSTSSISELECTDATADSP56002ADDRESSHOSTRD/WRREQTXRXHOSTSSIANALOGINPUTSELECTCODECDSP56002ANALOGOUTPUTTXRXHOSTSSISELECTDSP56002Figure 5-43 Multi-DSP Network ExampleMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 65Freescale Semiconductor, Inc.HOST INTERFACE (HI)5.3.6.5Host Port Usage Considerations – Host SideSynchronization is a common problem when two asynchronous systems are connected,and careful synchronization is required when reading multi-bit registers that are written byanother asynchronous system.
The considerations for proper operation are discussedbelow.Freescale Semiconductor, Inc...1. Unsynchronized Reading of Receive Byte Registers:When reading receive byte registers, RXH, RXM, or RXL, the host programmershould use interrupts or poll the RXDF flag which indicates that data is available. This guarantees that the data in the receive byte registers will be stable.2. Overwriting Transmit Byte Registers:The host programmer should not write to the transmit byte registers, TXH, TXM,or TXL, unless the TXDE bit is set, indicating that the transmit byte registers areempty. This guarantees that the DSP will read stable data when it reads theHRX register.3.
Synchronization of Status Bits from DSP to Host:HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set orcleared from inside the HI and read by the host processor. The host can readthese status bits very quickly without regard to the clock rate used by the DSP,but there is a chance that the state of the bit could be changing during the readoperation. This possible change is generally not a system problem, since thebit will be read correctly in the next pass of any host polling routine.However, if the host holds HEN for the minimum assertion time plus x clockcycles (see “Host Port Usage Considerations” in the DSP56002 Technical DataSheet (DSP56002/D) for the minimum number of cycles), the status data isguaranteed to be stable.
The x clock cycles are used to synchronize the HENsignal and block internal updates of the status bits. There is no other minimumHEN assertion time relationship to DSP clocks. There is a minimum HEN deassertion time so that the blocking latch can be updated if the host is in a tightpolling loop. This minimum time only applies to reading status bits.The only potential problem with the host processor’s reading of status bitswould be its reading HF3 and HF2 as an encoded pair. For example, if the DSPchanges HF3 and HF2 from “00” to “11”, there is a small possibility that the hostcould read the bits during the transition and receive “01” or “10” instead of “11”.If the combination of HF3 and HF2 has significance, the host processor could5 - 66PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)potentially read the wrong combination.
Two solutions would be to 1) read thebits twice and check for consensus, or 2) hold HEN access for HEN + x clockcycles so that status bit transitions are stabilized.Freescale Semiconductor, Inc...4. Overwriting the Host Vector:The host programmer should change the host vector register only when the HCbit is clear. This will guarantee that the DSP interrupt control logic will receive astable vector.5.
Cancelling a Pending Host Command Exception:The host processor may elect to clear the HC bit to cancel the host commandexception request at any time before it is recognized by the DSP. The DSP CPUmay execute the host exception after the HC bit is cleared because the hostprocessor does not know exactly when the exception will be recognized. Thisuncertainty in timing is due to differences in synchronization between the hostprocessor and DSP CPU and the uncertainties of pipelined exception processing. For this reason, the HV should not be changed at the same time the HC bitis cleared. However, the HV can be changed when the HC bit is set.6.
When using the HREQ pin for handshaking, wait until HREQ is asserted andthen start writing/reading data using the HEN pin or the HACK pin.When not using HREQ for handshaking, poll the INIT bit in the ICR to makesure it is cleared by the hardware (which means the INIT execution is completed). Then, start writing/reading data.If using neither HREQ for handshaking, nor polling the INIT bit, wait at least 6Tafter negation of HEN that wrote ICR, before writing/reading data. This waitensures that the INIT is completed, because it needs 3T for synchronization(worst case) plus 3T for executing the INIT.7. All unused input pins should be terminated. Also, any pin that is temporarilynot driven by an output during reset, when reprogramming a port or pin, whena bus is not driven, or at any other time, should be pulled up or down with aresistor.
For example, the HEN is capable of reacting to 2-ns noise spikeswhen it is not terminated. Allowing HACK to float may cause problems eventhough it is not needed in the circuit.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 67Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...HOST INTERFACE (HI)5 - 68PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SECTION 6Freescale Semiconductor, Inc...PORT CMOTOROLAFor More Information On This Product,Go to: www.freescale.com6-1Freescale Semiconductor, Inc.SECTION CONTENTSINTRODUCTION . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36.2GENERAL-PURPOSE I/O (PORT C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46.3SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . .
. . . . . . . . . . . . . . 6-116.4SYNCHRONOUS SERIAL INTERFACE (SSI) . . . . . . . . . . . . . . . . . . . . . . 6-76Freescale Semiconductor, Inc...6.16-2PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.INTRODUCTION6.1INTRODUCTIONFreescale Semiconductor, Inc...Port C is a triple-function I/O port with nine pins (see Figure 6-1). Three of the nine pinscan be configured as general-purpose I/O or as the serial communication interface (SCI)pins. The other six pins can also be configured as GPIO, or they can be configured as thesynchronous serial interface (SSI) pins.When configured as general-purpose I/O, port C can be used for device control. When thepins are configured as serial interfaces, port C provides a convenient connection to otherDSPs, processors, codecs, digital-to-analog and analog-to-digital converters, and any ofseveral transducers.
This section describes all three port C functions as well as examplesof how to configure and use each function.DEFAULTFUNCTIONALTERNATEFUNCTION16EXTERNAL ADDRESSSWITCHA0 - A15—D0 - D23—24EXTERNAL DATASWITCHPSDSX/YRDWRBNBRBGWTBSPORTAI/0(47)BUSCONTROL8HOST/DMAPARALLELINTERFACEPORTBI/0(15)SCIINTERFACEPORTCI/0(9)SSIINTERFACE——————————8PB0 - PB7PB8PB9PB10PB11PB12PB13PB14H0 - H7HA0HA1HA2HR/WHENHREQHACK or PB14PC0RXDPC1TXDPC2SCLKPC3SC0PC4SC1PC5SC2PC6SCKPC7SRDPC8STDFigure 6-1 Port C InterfaceMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6-3Freescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)6.2GENERAL-PURPOSE I/O (PORT C)When it is configured as GPIO, Port C can be viewed as nine I/O pins (see Figure 6-2),which are controlled by three memory-mapped registers.
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