Сигнальный МП Motorola DSP56002 (1086189), страница 34
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This feature allows DSP programmers to use the SCI baudclock generator as a simple periodic interrupt generator if the SCI is not in use, if externalclocks are used for the SCI, or if periodic interrupts are needed at the SCI baud rate. TheSCI internal clock is divided by 16 (to match the 1 × SCI baud rate) for timer interrupt generation. This timer does not require that any SCI pins be configured for SCI use to operate.TMIE is cleared by hardware and software reset.6.3.2.1.13SCR SCI Timer Interrupt Rate (STIR) Bit 14This bit controls a divide by 32 in the SCI Timer interrupt generator.
When this bit iscleared, the divide by 32 is inserted in the chain. When the bit is set, the divide by 32 isbypassed, thereby increasing the timer resolution by 32 times. This bit is cleared by hardware and software reset.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 21Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...SERIAL COMMUNICATION INTERFACE (SCI)6.3.2.1.14SCR SCI Clock Polarity (SCKP) Bit 15The clock polarity, sourced or received on the clock pin (SCLK), can be inverted using thisbit, eliminating the need for an external inverter. When bit 15 equals zero, the clock polarity is positive; when bit 15 equals one, the clock polarity is negative. In the synchronousmode, positive polarity means that the clock is normally positive and transitions negativeduring data valid; whereas, negative polarity means that the clock is normally negativeand transitions positive during valid data.
In the asynchronous mode, positive polaritymeans that the rising edge of the clock occurs in the center of the period that data is valid;negative polarity means that the falling edge of the clock occurs during the center of theperiod that data is valid. SCKP is cleared on hardware and software reset.6.3.2.2SCI Status Register (SSR)The SSR is an 8-bit read-only register used by the DSP CPU to determine the status ofthe SCI.
When the SSR is read onto the internal data bus, the register contents occupythe low-order byte of the data bus and all high-order portions are zero filled. The statusbits are described in the following paragraphs.6.3.2.2.1SSR Transmitter Empty (TRNE) Bit 0The TRNE flag is set when both the transmit shift register and data register are empty toindicate that there is no data in the transmitter. When TRNE is set, data written to one ofthe three STX locations or to the STXA will be transferred to the transmit shift register andbe the first data transmitted. TRNE is cleared when TDRE is cleared by writing data intothe transmit data register (STX) or the transmit data address register (STXA), or when anidle, preamble, or break is transmitted. The purpose of this bit is to indicate that the transmitter is empty; therefore, the data written to STX or STXA will be transmitted next – i.e.,there is not a word in the transmit shift register presently being transmitted.
This procedure is useful when initiating the transfer of a message (i.e., a string of characters). TRNEis set by the hardware, software, SCI individual, and stop reset.6.3.2.2.2SSR Transmit Data Register Empty (TDRE) Bit 1The TDRE bit is set when the SCI transmit data register is empty. When TDRE is set, newdata may be written to one of the SCI transmit data registers (STX) or transmit data address register (STXA). TDRE is cleared when the SCI transmit data register is written.TDRE is set by the hardware, software, SCI individual, and stop reset.In the SCI synchronous mode, when using the internal SCI clock, there is a delay of up to5.5 serial clock cycles between the time that STX is written until TDRE is set, indicatingthe data has been transferred from the STX to the transmit shift register.
There is a twoto four serial clock cycle delay between writing STX and loading the transmit shift register;6 - 22PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)in addition, TDRE is set in the middle of transmitting the second bit.
When using an external serial transmit clock, if the clock stops, the SCI transmitter stops. TDRE will not be setuntil the middle of the second bit transmitted after the external clock starts. Gating the external clock off after the first bit has been transmitted will delay TDRE indefinitely.Freescale Semiconductor, Inc...In the SCI asynchronous mode, the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the transmit shift register nor when the word first beginsto be shifted out.
TDRE is set two cycles of the 16× clock after the start bit – i.e., two 16×clock cycles into to transmission time of the first data bit.6.3.2.2.3SSR Receive Data Register Full (RDRF) Bit 2The RDRF bit is set when a valid character is transferred to the SCI receive data registerfrom the SCI receive shift register. RDRF is cleared when the SCI receive data register isread or by the hardware, software, SCI individual, and stop reset.6.3.2.2.4SSR Idle Line Flag (IDLE) Bit 3IDLE is set when 10 (or 11) consecutive ones are received. IDLE is cleared by a start-bitdetection. The IDLE status bit represents the status of the receive line.
The transition ofIDLE from zero to one can cause an IDLE interrupt (ILIE). IDLE is cleared by the hardware, software, SCI individual, and stop reset.6.3.2.2.5SSR Overrun Error Flag (OR) Bit 4The OR flag is set when a byte is ready to be transferred from the receive shift register tothe receive data register (SRX) that is already full (RDRF=1). The receive shift registerdata is not transferred to the SRX. The OR flag indicates that character(s) in the receivedata stream may have been lost. The only valid data is located in the SRX.
OR is clearedwhen the SCI status register is read, followed by a read of SRX. The OR bit clears the FEand PE bits – i.e., overrun error has higher priority than FE or PE. OR is cleared by thehardware, software, SCI individual, and stop reset.6.3.2.2.6SSR Parity Error (PE) Bit 5In the 11-bit asynchronous modes, the PE bit is set when an incorrect parity bit has beendetected in the received character. It is set simultaneously with RDRF for the byte whichcontains the parity error – i.e., when the received word is transferred to the SRX.
If PE isset, it does not inhibit further data transfer into the SRX. PE is cleared when the SCI statusregister is read, followed by a read of SRX. PE is also cleared by the hardware, software,SCI individual, or stop reset. In the 10-bit asynchronous mode, the 11-bit multidrop mode,MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 23Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...and the 8-bit synchronous mode, the PE bit is always cleared since there is no parity bitin these modes. If the byte received causes both parity and overrun errors, the SCI receiver will only recognize the overrun error.6.3.2.2.7SSR Framing Error Flag (FE) Bit 6The FE bit is set in the asynchronous modes when no stop bit is detected in the data stringreceived. FE and RDRE are set simultaneously – i.e., when the received word is transferred to the SRX.
However, the FE flag inhibits further transfer of data into the SRX untilit is cleared. FE is cleared when the SCI status register is read followed by reading theSRX. The hardware, software, SCI individual, and stop reset also clear FE. In the 8-bitsynchronous mode, FE is always cleared. If the byte received causes both framing andoverrun errors, the SCI receiver will only recognize the overrun error.6.3.2.2.8SSR Received Bit 8 Address (R8) Bit 7In the 11-bit asynchronous multidrop mode, the R8 bit is used to indicate whether the received byte is an address or data. R8 is not affected by reading the SRX or status register.The hardware, software, SCI individual, and stop reset clear R8.6.3.2.3SCI Clock Control Register (SCCR)The SCCR is a 16-bit read/write register which controls the selection of the clock modesand baud rates for the transmit and receive sections of the SCI interface.
The control bitsare described in the following paragraphs. The SCCR is cleared by hardware reset.The basic points of the clock generator are as follows:1.The SCI core always uses a 16 × internal clock in the asynchronous modesand always uses a 2 × internal clock in the synchronous mode. The maximuminternal clock available to the SCI peripheral block is the oscillator frequencydivided by 4. With a 40-MHz crystal, this gives a maximum data rate of 625Kbps for asynchonous data and 5 Mbps for synchronous data.
These maximum rates are the same for internally or externally supplied clocks.2.The 16 × clock is necessary for the asynchronous modes to synchronize theSCI to the incoming data (see Figure 6-11).3.For the asynchronous modes, the user must provide a 16 × clock if he wishesto use an external baud rate generator (i.e., SCLK input).4.For the asynchronous modes, the user may select either 1 × or 16 × for theoutput clock when using internal TX and RX clocks (TCM=0 and RCM=0).6 - 24PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.Freescale Semiconductor, Inc...SERIAL COMMUNICATION INTERFACE (SCI)5.The transmit data on the TXD pin changes on the negative edge of the 1 ×serial clock and is stable on the positive edge (SCKP=0). For SCKP equalsone, the data changes on the positive edge and is stable on the negativeedge.6.The receive data on the RXD pin is sampled on the positive edge (if SCKP=0)or on the negative edge (if SCKP=1) of the 1 × serial clock.7.For the asynchronous mode, the output clock is continuous.8.For the synchronous mode, a 1 × clock is used for the output or input baudrate.
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