Сигнальный МП Motorola DSP56002 (1086189), страница 37
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This interrupt is enabled by SCRbit 11 (RIE).3. SCI Transmit Data – caused by transmit data register empty. This error-freeinterrupt may use a fast interrupt service routine for minimum overhead. Thisinterrupt is enabled by SCR bit 12 (TIE).4. SCI Idle Line – occurs when the receive line enters the idle state (10 or 11 bitsof ones). This interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt is enabled by SCR bit 10 (ILIE).5. SCI Timer – caused by the baud rate counter underflowing. This interrupt isautomatically reset when the interrupt is accepted. This interrupt is enabled bySCR bit 13 (TMIE).6.3.6Synchronous DataThe synchronous mode (WDS=0, shift register mode) is designed to implement serial-to-parallel and parallel-to-serial conversions.
This mode will directly interface to8051/8096 synchronous (mode 0) buses as both a controller (master) or a peripheral(slave) and is compatible with the SSI mode if SCKP equals one. In synchronous mode,the clock is always common to the transmit and receive shift registers.As a controller (synchronous master) shown in Figure 6-17, the DSP puts out a clock onthe SCLK pin when data is present in the transmit shift register (a gated clock mode). Themaster mode is selected by choosing internal transmit and receive clocks (setting TCMand RCM=0). The example shows a 74HC165 parallel-to-serial shift register and74HC164 serial-to-parallel shift register being used to convert eight bits of serial I/O toeight bits of parallel I/O.
The load pulse latches eight bits into the 74HC165 and thenSCLK shifts the RXD data into the SCI (these data bits are sample bits 0-7 in the timingdiagram). At the same time, TXD shifts data out (B0-B7) to the 74HC164. When using theinternal clock, data is transmitted when the transmit shift register is full. Data is valid onboth edges of the output clock, which is compatible with an 8051 microprocessor.
Received data is sampled in the middle of the clock low time if SCKP equals zero or in themiddle of the clock high time if SCKP equals one. There is a window during which STXmust be written with the next byte to be transmitted to prevent a gap between words. ThisMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 396 - 40X:$FFF2X:$FFF0STIR140RCMSCKP150TCMRECEIVE DATATRANSMIT DATA(SSFTD = 0)COD12TIE12SAMPLEXXXXXXSCP13TMIE13CLOCK OUTPUT(SCP = 0)1415For More Information On This Product,Go to: www.freescale.comPORT CXX1B1CD1010ILIE10XXCD99TE92B2XXCD88RE8TXDSCLKRXDDSP560023CLKCLKQLDXX4XXCD55WAKE55B5026B6CD33XXCD22SSFTD WDS203B7700CD00XXXXXXXCD118 PARALLEL OUTPUTSLOAD PULSE01WDS1 WDS08 PARALLEL INPUTSXXCD44SBK4Figure 6-17 Synchronous Master74HC164S/PDQB4CD66RWU6WRITE STXB3CD77WOMS774HC165EXAMPLE: SHIFT REGISTER I/O0B0CD1111RIE11Freescale Semiconductor, Inc...SCI CLOCK CONTROL REGISTER (SCCR)(READ/WRITE)SCI CONTROL REGISTER (SCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...window is from the time TDRE goes high halfway into transmission of bit 1 until the middleof bit 6 (see Figure 6-19(a)).As a peripheral (synchronous slave) shown in Figure 6-18, the DSP accepts an input clockfrom the SCLK pin.
If SCKP equals zero, data is clocked in on the rising edge of SCLK,and data is clocked out on the falling edge of SCLK. If SCKP equals one, data is clockedin on the falling edge of SCLK, and data is clocked out on the rising edge of SCLK. Theslave mode is selected by choosing external transmit and receive clocks (TCM andRCM=1). Since there is no frame signal, if a clock is missed due to noise or any other reason, the receiver will lose synchronization with the data without any error signal being generated. Detecting an error of this type can be done with an error detecting protocol or withexternal circuitry such as a watchdog timer. The simplest way to recover synchronizationis to reset the SCI.The timing diagram in Figure 6-18 shows transmit data in the normal driven mode.
Bit B7is essentially one-half SCI clock long (TSCI/2 + 1.5 TEXTAL) The last data bit is truncatedso that the pin is guaranteed to go to its reset state before the start of the next data word,thereby delimiting data words. The 1.5 crystal clock cycles provide sufficient hold time tosatisfy most external logic requirements. The example diagram requires that the WOMSbit be set in the SCR to wired-OR RXD and TXD, which causes TXD to be three-statedwhen not transmitting.
Collisions (two devices transmitting simultaneously) must be avoided with this circuit by using a protocol such as alternating transmit and receive periods. Inthe example, the 8051 is the master device because it controls the clock. There is a window during which STX must be written with the next byte to be transmitted to prevent thecurrent word from being retransmitted. This window is from the time TDRE goes high,which is halfway into the transmission of bit 1, until the middle of bit 6 (see Figure 6-19(b)).Of course, this assumes the clock remains continuous – i.e., there is a second word.
If theclock stops, the SCI stops.The DSP is initially configured according to the protocol to either receive data or transmit data.If the protocol determines that the next data transfer will be a DSP transmit, the DSP will configure the SCI for transmit and load STX (or STXA). When the master starts SCLK, data willbe ready and waiting. If the protocol determines that the next data transfer will be a DSP receive, the DSP will configure the SCI for receive and will either poll the SCI or enable interrupts. This methodology allows multiple slave processors to use the same data line. Selectionof individual slave processors can be under protocol control or by multiplexing SCLK.Note: TCM=0, RCM=1 and TCM=1,RCM=0 are not allowed in the synchronous mode.The results are undefined.The assembly program shown in Figure 6-20 uses the SCI synchronous mode to transmitonly the low byte of the Y data ROM contents.
The program sets the reset vector to runthe program after a hardware reset, puts the MOVEP instruction at the SCI transmit interMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 416 - 42X:$FFF2X:$FFF0STIR141RCMSCKP151TCM13RECEIVE DATATRANSMIT DATA(SSFTD = 0)COD12TIE12For More Information On This Product,Go to: www.freescale.comPORT C0B0XXCD1111RIE111B1CD1010ILIE10XXCD99TE92B2XXCD88RE8B4CD66RWU63XX4WRITE STXB3CD77WOMS7XXCD55WAKE5XXCD4402P3.1P3.06B6CD33OR809670100SCI CLOCK CONTROL REGISTER (SCCR)(READ/WRITE)SCI CONTROL REGISTER (SCR)(READ/WRITE)1.5 tcycCD00XXXXXXXCD11WDS1 WDS0B78051XXCD22SSFTD WDS203Figure 6-18 Synchronous SlaveSCLKTXDRXDDSP5600254SBKB5EXAMPLE: INTERFACE TO SYNCHRONOUS MICROCOMPUTER BUSESSAMPLEXXXXXXSCP13TMIECLOCK INPUT(SKP = 0)1415Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAMOTOROLASTX WRITE RANGEBIT 0MAX 5.5 SERIAL CLOCK CYCLESBIT 1BIT 2BIT 4BIT 50 BY STX WRITEFIRST WORDBIT 3TDRESTX WRITE RANGE FOR NOGAP BETWEEN WORDS 1 AND 2For More Information On This Product,Go to: www.freescale.comPORT CSTX WRITE RANGEBIT 0BIT 1BIT 2BIT 4BIT 50 BY STX WRITEFIRST WORDBIT 3TDRESTX WRITE RANGEFigure 6-19 Synchronous Timing(b) SlaveNOTE: In external clock mode, if data 2 is written after the middle of bit 6 of data 1, then the previous data is retransmitted anddata 2 is transmitted after the retransmission of data 1.TXD(TRANSMIT DATA)TRDESTXWRITERANGESERIALCLOCK(EXT)SYNCHRONOUS MODE, INTERNAL CLOCK (SLAVE)(a) MasterNOTE: In internal clock mode, if data 2 is written after the middle of bit 6 of data 1, then a gap of at least two serial bits is insertedbetween word 1 and word 2.
The gap is bigger as STX is written later.TXD(TRANSMIT DATA)TRDESTXWRITERANGESERIALCLOCK(INT)SYNCHRONOUS MODE, INTERNAL CLOCK (MASTER)BIT 6BIT 6BIT 7BIT 7Freescale Semiconductor, Inc...BIT 0BIT 0BIT 2BIT 2SECOND WORDBIT 1SECOND WORDBIT 1Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)rupt vector location, sets the memory wait states to zero, and configures the memory6 - 43Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...SERIAL COMMUNICATION INTERFACE (SCI)ORGJMPORGMOVEPP:0$40P:$18Y:(R0)+,X:$FFF4;Reset vector;;SCI transmit interrupt vector;Transmit low byte of dataORGMOVEPMOVEMOVEMOVECMOVEPMOVEPMOVEPMOVECLAB0 JMPP:$40#0,X:$FFFE#$100,R0#$FF,M0#6,OMR#$C000,X:$FFFF#$1200,X:$FFF0#7,X:$FFE1#0,SRLAB0;Clear BCR;Data ROM start address;Size of data ROM - Wraps around at $200;Change operating mode to enable data ROM;Interrupt priority register;8-bit synchronous mode;Port C control register – enable SCI;Unmask interrupts;Wait in loop for interruptsFigure 6-20 SCI Synchronous Transmitpointers, operating mode register, and the IPR.The SCI is then configured and the interrupts are unmasked, which starts the data transfer.
The jump-to-self instruction (LAB0 JMP LAB0) is used to wait while interrupts transferthe data.The program shown in Figure 6-21 is the program for receiving data from the program presented in Figure 6-20. The program sets the reset vector to run the program after hardware reset, puts the MOVEP instruction to store the data in a circular buffer starting at$100 at the SCI receive interrupt vector location, puts another MOVEP instruction at theSCI receive interrupt vector location, sets the memory wait states to zero, and configuresthe memory pointers and IPR.
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