Сигнальный МП Motorola DSP56002 (1086189), страница 26
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The first step is to initialize the DSPTO IRQBDSP56002MC68440IRQ+5 V+5 VCIDQREQ0HREQ+5 VACK0HACKA0A1ASOWNBURSTREQ0FAST INTERRUPTTO TRANSFER 24-BIT WORD8THACKHIGHBYTEMIDDLEBYTELOWBYTEHIGHBYTEDMA ACK GATED OFF1 DMA CYCLE = 8T = 4 DMA CLOCK CYCLESMAX. MC68440 CLOCK = 10 MHz = > T = 50 nsFigure 5-18 DMA Transfer Logic and Timing5 - 38PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...STEP 1THE DSP CPU INITIALIZES THE DSP SIDE OFTHE HI BY WRITING:1) HCR AT X:$FFE8 AND2) PBC AT X:$FFE0STEP 2THE HOST PROCESOR INITIALIZES THEHOST SIDE OF THE HI BY WRITING:1) ICR AT $0 AND/OR2) CVR AT $1 AND/OR3) IVR AT $3Figure 5-19 HI Initialization Flowchartside of the HI, which requires that the options for interrupts and flags be selected and thenthe HI be selected (see Figure 5-20).
The second step is for the host processor to clearthe HC bit by writing the CVR, select the data transfer method - polling, interrupts, or DMA(see Figure 5-21 (d) and Figure 5-23), and write the IVR in the case of a MC680XX Familyhost processor. Figure 5-19 through Figure 5-22 provide a general description of how toinitialize the HI.
Later paragraphs in this section provide more detailed descriptions forspecific examples.These subsections include some code fragments illustrating how to initialize and transfer data using the HI.5.3.6.2Polling/Interrupt Controlled Data TransferHandshake flags are provided for polled or interrupt-driven data transfers. Because theDSP interrupt response is sufficiently fast, most host microprocessors can load or storedata at their maximum programmed I/O (non-DMA) instruction rate without testing thehandshake flags for each transfer. If the full handshake is not needed, the host processorcan treat the DSP as fast memory, and data can be transferred between the host and DSPat the fastest host processor rate.
DMA hardware may be used with the external hostrequest and host acknowledge pins to transfer data at the maximum DSP interrupt rate.The basic data transfer process from the host processor’s view (see Figure 5-15) is forthe host to:1.2.3.4.Assert HREQ when the HI is ready to transfer dataAssert HACK If the interface is using HACKAssert HR/W to select whether this operation will read or write a registerAssert the HI address (HA2, HA1, and HA0) to select the register to be read or writtenMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 39Freescale Semiconductor, Inc.HOST INTERFACE (HI)5.
Assert HEN to enable the HI6. When HEN is deasserted, the data can be latched or read as appropriate if thetiming requirements have been observed7. HREQ will be deasserted if the operation is completeSTEP 1 OF HOST PORT CONFIGURATIONFreescale Semiconductor, Inc...1. ENABLE/DISABLEHOST RECEIVE DATA FULL INTERRUPTENABLE INTERRUPT: BIT 0 = 1DISABLE INTERRUPT: BIT 0 = 02, ENABLE/DISABLEHOST TRANSMIT DATA EMPTY INTERRUPTENABLE INTERRUPT: BIT 1 = 1DISABLE INTERRUPT: BIT 1 = 03. ENABLE/DISABLEHOST COMMAND PENDING INTERRUPTENABLE INTERRUPT: BIT 2 = 1DISABLE INTERRUPT: BIT 2 = 04.
SET/CLEARHOST FLAG 2 (OPTIONAL)ENABLE FLAG: BIT 3 = 1DISABLE FLAG: BIT 3 = 05. SET/CLEARHOST FLAG 3 (OPTIONAL)ENABLE FLAG: BIT 4 = 1DISABLE FLAG: BIT 4 = 07X:$FFE8*6*543*HF3HF2210HCIE HTIE HRIEHOST CONTROL REGISTER (HCR)(READ/WRITE)6. SELECT PORT B FOR HOST PORT OPERATION:15X:$FFE0* * * *0* * * * * * * * * *BC BC10* Reserved; write as zero.NOTE: The host flags are general-purpose semaphores.
They are not required for host port operationbut may be used in some applications.Figure 5-20 HI Initialization–DSP Side5 - 40PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)STEP 2 OF HOST PORT CONFIGURATION1. CLEAR HOST COMMAND BIT (HC):BIT 7 = 07$16HC50COMMAND VECTOR REGISTER (CVR)(READ/WRITE)HV*Freescale Semiconductor, Inc...*Reserved; write as zero.2. OPTION 1: SELECT HOST VECTOR (HV)(OPTIONAL SINCE HV CAN BE SET ANY TIME BEFORE THE HOST COMMAND IS EXECUTED.
DSP INTERRUPT VECTOR = THE HOSTVECTOR MULTIPLIED BY 2. DEFAULT (UPON DSP RESET): HV = $12 ➞ DSP INTERRUPT VECTOR $0024Figure 5-21 (a) HI Configuration–Host SideSTEP 2 OF HOST PORT CONFIGURATION2. OPTION 2: SELECT POLLING MODE FOR HOST TO DSP COMMUNICATIONINITIALIZE DSPAND HOST PORTDMA OFFBIT 5 = 0BIT 6 = 07$0INIT6HM1DISABLE INTERRUPTSBIT 0 = 0BIT 1 = 0OPTIONAL54HM0HF132HF0*10TREQ RREQINTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)*Reserved; write as zero.Figure 5-21 (b) HI Initialization–Host Side, Polling ModeThe previous transfer description is an overview. Specific and exact information for the HIdata transfers and their timing can be found in Section 5.3.6.3 DMA Data Transfer andin the DSP56002 Advance Information Data Sheet (DSP56002/D).5.3.6.2.1Host to DSP - Data TransferFigure 5-23 shows the bits in the ISR and ICR registers used by the host processor and thebits in the HSR and HCR registers used by the DSP to transfer data from the host processor tothe DSP.
The registers shown are the status register and control register as they are seen bythe host processor, and the status register and control register as they are seen by the DSP.Only the registers used to transmit data from the host processor to the DSP areMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 41Freescale Semiconductor, Inc.HOST INTERFACE (HI)STEP 2 OF HOST PORT CONFIGURATION2. OPTION 3: SELECT INTERRUPT MODE FORDSP TO HOSTORHOST TO DSPINITIALIZE DSPINITIALIZE HI**BIT 7 = 1DSP TO HOSTANDHOST TO DSPOPTIONALFreescale Semiconductor, Inc...ENABLETRANSMIT DATA EMPTY INTERRUPTBIT 0 = 0BIT 1 = 1ORDMA OFFBIT 5 = 0BIT 6 = 0$0ENABLERECEIVE DATA FULL INTERRUPTBIT 0 = 1BIT 1 = 0765432INITHM1HM0HF1HF0*1ENABLERECEIVE DATA FULL INTERRUPT ANDTRANSMIT DATA EMPTY INTERRUPTBIT 0 = 1BIT 1 = 10TREQ RREQINTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)2.
OPTION 4: LOAD HOST INTERRUPT VECTOR IF USING THE INTERRUPT MODE AND THE HOST PROCESSOR REQUIRES ANINTERRUPT VECTOR.$376543210IV7IV6IV5IV4IV3IV2IV1IV0INTERRUPT VECTOR REGISTER (IVR)(READ/WRITE)*Reserved; write as zero.**See Figure 10 - 23.Figure 5-21 (c) HI Initialization–Host Side, Interrupt Modedescribed. Figure 5-24 illustrates the process of that data transfer.
The steps in Figure 524 can be summarized as follows:1.2.3.4.5.6.5 - 42When the TXDE bit in the ISR is set, it indicates that the HI is ready to receivea data byte from the host processor because the transmit byte registers (TXH,TXM, TXL) are empty.The host processor can poll as shown in this step.Alternatively, the host processor can use interrupts to determine the status ofthis bit.
Setting the TREQ bit in the ICR causes the HREQ pin to interrupt thehost processor when TXDE is set.Once the TXDE bit is set, the host can write data to the HI. It does this by writing three bytes to TXH, TXM, and TXL, respectively, or two bytes to TXM andTXL, respectively, or one byte to TXL.Writing data to TXL clears TXDE in the ISR.From the DSP’s viewpoint, the HRDF bit (when set) in the HSR indicates thatdata is waiting in the HI for the DSP.PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)7.When the DSP reads the HRX, the HRDF bit is automatically cleared andTXDE in the ISR is set.When TXDE=0 and HRDF=0, data is automatically transferred from TBR toHRX which sets HRDF.The DSP can poll HRDF to see when data has arrived, or it can use interrupts.If HRIE (in the HCR) and HRDF are set, exception processing is started usinginterrupt vector P:$0020.8.Freescale Semiconductor, Inc...9.10.The code shown in Figure 5-25 is an excerpt from the Host I/O Port Technical Bulletin (inhouse document).
The MAIN PROGRAM initializes the HI and then hangs in a wait loopwhile it allows interrupts to transfer data from the host processor to the DSP. The firstthree MOVEP instructions enable the HI and configure the interrupts. The followingMOVE enables the interrupts (this should always be done after the interrupt programs andhardware are completely initialized) and prepares the DSP CPU to look for the host flag,HF0=1. The JCLR instruction is a polling loop that looks for HF0=1, which indicates thatthe host processor is ready. When the host processor is ready to transfer data to the DSP,the DSP enables HRIE in the HCR, which allows the interrupt routine to receive data fromthe host processor.
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