ATmega128 (961723), страница 54
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(Activelow)11DescriptionRecommended Inputwhen notin UseOutput Values whenRecommended Inputsare Used, and CPU isnot Using the ADC2652467M–AVR–11/04Table 104. Boundary-scan Signals for the ADC (Continued)SignalNameDirectionas Seenfrom theADCSCTESTInputSwitch-cap TESTenable. Output fromx10 gain stage sendout to Port Pin havingADC_400STInputOutput of gain stageswill settle faster if thissignal is high first twoACLK periods afterAMPEN goes high.00VCCRENInputSelects Vcc as theACC referencevoltage.00Note:DescriptionRecommended Inputwhen notin UseOutput Values whenRecommended Inputsare Used, and CPU isnot Using the ADCIncorrect setting of the switches in Figure 131 will make signal contention and may damage the part.
There are several input choices to the S&H circuitry on the negative input ofthe output comparator in Figure 131. Make sure only one path is selected from either oneADC pin, Bandgap reference source, or Ground.If the ADC is not to be used during scan, the recommended input values from Table 104should be used. The user is recommended not to use the Differential Gain stages during scan. Switch-Cap based gain stages require fast operation and accurate timingwhich is difficult to obtain when used in a scan chain. Details concerning operations ofthe differential gain stage is therefore not provided.The AVR ADC is based on the analog circuitry shown in Figure 131 with a successiveapproximation algorithm implemented in the digital logic.
When used in Boundary-scan,the problem is usually to ensure that an applied analog voltage is measured within somelimits. This can easily be done without running a successive approximation algorithm:apply the lower limit on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify theoutput from the comparator to be high.The ADC need not be used for pure connectivity testing, since all analog inputs areshared with a digital port pin as well.When using the ADC, remember the following•The Port Pin for the ADC channel in use must be configured to be an input with pullup disabled to avoid signal contention.•In normal mode, a dummy conversion (consisting of 10 comparisons) is performedwhen enabling the ADC.
The user is advised to wait at least 200ns after enabling theADC before controlling/observing any ADC signal, or perform a dummy conversionbefore using the first result.•The DAC values must be stable at the midpoint value 0x200 when having the HOLDsignal low (Sample mode).As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3when the power supply is 5.0V and AREF is externally connected to VCC.The lower limit is:The upper limit is:2661024 ⋅ 1.5V ⋅ 0,95 ⁄ 5V = 291 = 0x1231024 ⋅ 1.5V ⋅ 1.05 ⁄ 5V = 323 = 0x143ATmega1282467M–AVR–11/04ATmega128The recommended values from Table 104 are used unless other values are given in thealgorithm in Table 105. Only the DAC and Port Pin values of the Scan Chain are shown.The column “Actions” describes what JTAG instruction to be used before filling theBoundary-scan Register with the succeeding columns. The verification should be doneon the data scanned out when scanning in the data on the same row in the table.Table 105.
Algorithm for Using the ADCPA3.StepActionsADCENDACMUXENHOLDPRECHPA3.Data1SAMPLE_PRELOAD10x2000x08110002EXTEST10x2000x0801000310x2000x0811000410x1230x0811000510x1230x081000010x2000x0811000710x2000x0801000810x2000x0811000910x1430x08110001010x1430x081000010x2000x0811000611Verify theCOMP bitscannedout to be 0Verify theCOMP bitscannedout to be 1PA3.ControlPullup_EnableUsing this algorithm, the timing constraint on the HOLD signal constrains the TCK clockfrequency.
As the algorithm keeps HOLD high for five steps, the TCK clock frequencyhas to be at least five times the number of scan bits divided by the maximum hold time,thold,max2672467M–AVR–11/04ATmega128 Boundaryscan OrderTable 106 shows the Scan order between TDI and TDO when the Boundary-scan Chainis selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bitscanned out. The scan order follows the pin-out order as far as possible. Therefore, thebits of Port A is scanned in the opposite bit order of the other ports. Exceptions from therules are the Scan chains for the analog circuits, which constitute the most significantbits of the scan chain regardless of which physical pin they are connected to.
In Figure124, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn.Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain,since these pins constitute the TAP pins when the JTAG is enabled.Table 106. ATmega128 Boundary-scan Order268Bit NumberSignal NameModule204AC_IDLEComparator203ACO202ACME201AINBG200COMPADC(1)199PRIVATE_SIGNAL1198ACLK197ACTEN196PRIVATE_SIGNAL1(2)195ADCBGEN194ADCEN193AMPEN192DAC_9191DAC_8190DAC_7189DAC_6188DAC_5187DAC_4186DAC_3185DAC_2184DAC_1183DAC_0182EXTCH181G10180G20179GNDEN178HOLD177IREFEN176MUXEN_7ATmega1282467M–AVR–11/04ATmega128Table 106.
ATmega128 Boundary-scan Order (Continued)Bit NumberSignal NameModule175MUXEN_6ADC174MUXEN_5173MUXEN_4172MUXEN_3171MUXEN_2170MUXEN_1169MUXEN_0168NEGSEL_2167NEGSEL_1166NEGSEL_0165PASSEN164PRECH163SCTEST162ST161VCCREN160PENProgramming enable (observe only)159PE0.DataPort E158PE0.Control157PE0.Pullup_Enable156PE1.Data155PE1.Control154PE1.Pullup_Enable153PE2.Data152PE2.Control151PE2.Pullup_Enable150PE3.Data149PE3.Control148PE3.Pullup_Enable147PE4.Data146PE4.Control145PE4.Pullup_Enable144PE5.Data143PE5.Control142PE5.Pullup_Enable141PE6.Data140PE6.Control2692467M–AVR–11/04Table 106. ATmega128 Boundary-scan Order (Continued)270Bit NumberSignal NameModule139PE6.Pullup_EnablePort E138PE7.Data137PE7.Control136PE7.Pullup_Enable135PB0.Data134PB0.Control133PB0.Pullup_Enable132PB1.Data131PB1.Control130PB1.Pullup_Enable129PB2.Data128PB2.Control127PB2.Pullup_Enable126PB3.Data125PB3.Control124PB3.Pullup_Enable123PB4.Data122PB4.Control121PB4.Pullup_Enable120PB5.Data119PB5.Control118PB5.Pullup_Enable117PB6.Data116PB6.Control115PB6.Pullup_Enable114PB7.Data113PB7.Control112PB7.Pullup_Enable111PG3.Data110PG3.Control109PG3.Pullup_Enable108PG4.Data107PG4.Control106PG4.Pullup_Enable105TOSC104TOSCONPort BPort G32 kHz Timer OscillatorATmega1282467M–AVR–11/04ATmega128Table 106.
ATmega128 Boundary-scan Order (Continued)Bit NumberSignal NameModule103RSTT102RSTHVReset Logic(Observe-only)101EXTCLKENEnable signals for main Clock/Oscillators100OSCON99RCOSCEN98OSC32EN97EXTCLK (XTAL1)96OSCCK95RCCK94OSC32CK93TWIENTWI92PD0.DataPort D91PD0.Control90PD0.Pullup_Enable89PD1.Data88PD1.Control87PD1.Pullup_Enable86PD2.Data85PD2.Control84PD2.Pullup_Enable83PD3.Data82PD3.Control81PD3.Pullup_Enable80PD4.Data79PD4.Control78PD4.Pullup_Enable77PD5.Data76PD5.Control75PD5.Pullup_Enable74PD6.Data73PD6.Control72PD6.Pullup_Enable71PD7.Data70PD7.Control69PD7.Pullup_Enable68PG0.DataClock input and Oscillators for the main clock(Observe-only)Port G2712467M–AVR–11/04Table 106.
ATmega128 Boundary-scan Order (Continued)272Bit NumberSignal NameModule67PG0.ControlPort G66PG0.Pullup_Enable65PG1.Data64PG1.Control63PG1.Pullup_Enable62PC0.Data61PC0.Control60PC0.Pullup_Enable59PC1.Data58PC1.Control57PC1.Pullup_Enable56PC2.Data55PC2.Control54PC2.Pullup_Enable53PC3.Data52PC3.Control51PC3.Pullup_Enable50PC4.Data49PC4.Control48PC4.Pullup_Enable47PC5.Data46PC5.Control45PC5.Pullup_Enable44PC6.Data43PC6.Control42PC6.Pullup_Enable41PC7.Data40PC7.Control39PC7.Pullup_Enable38PG2.Data37PG2.Control36PG2.Pullup_Enable35PA7.Data34PA7.Control33PA7.Pullup_Enable32PA6.DataPort CPort GPort AATmega1282467M–AVR–11/04ATmega128Table 106.
ATmega128 Boundary-scan Order (Continued)Bit NumberSignal NameModule31PA6.ControlPort A30PA6.Pullup_Enable29PA5.Data28PA5.Control27PA5.Pullup_Enable26PA4.Data25PA4.Control24PA4.Pullup_Enable23PA3.Data22PA3.Control21PA3.Pullup_Enable20PA2.Data19PA2.Control18PA2.Pullup_Enable17PA1.Data16PA1.Control15PA1.Pullup_Enable14PA0.Data13PA0.Control12PA0.Pullup_Enable11PF3.Data10PF3.Control9PF3.Pullup_Enable8PF2.Data7PF2.Control6PF2.Pullup_Enable5PF1.Data4PF1.Control3PF1.Pullup_Enable2PF0.Data1PF0.Control0Notes:Port FPF0.Pullup_Enable1. PRIVATE_SIGNAL1 should always scanned in as zero.2. PRIVATE_SIGNAL2 should always scanned in as zero.2732467M–AVR–11/04Boundary-scanDescription LanguageFiles274Boundary-scan Description Language (BSDL) files describe Boundary-scan capabledevices in a standard format used by automated test-generation software.
The orderand function of bits in the Boundary-scan Data Register are included in this description.ATmega1282467M–AVR–11/04ATmega128Boot Loader Support– Read-While-WriteSelf-ProgrammingThe Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This featureallows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available datainterface and associated protocol to read code and write (program) that code into theFlash memory, or read the code from the program memory.
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