ATmega128 (961723), страница 50
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Theresult is presented in two’s complement form, from 0x200 (-512d) through 0x1FF(+511d). Note that if the user wants to perform a quick polarity check of the results, it issufficient to read the MSB of the result (ADC9 in ADCH). If this bit is one, the result isnegative, and if this bit is zero, the result is positive. Figure 119 shows the decoding ofthe differential input range.Table 96 shows the resulting output codes if the differential input channel pair (ADCn ADCm) is selected with a gain of GAIN and a reference voltage of VREF.242ATmega1282467M–AVR–11/04ATmega128Figure 119. Differential Measurement RangeOutput Code0x1FF0x000- V REF/GAIN0x3FF0VREF/GAINDifferential InputVoltage (Volts)0x200Table 96. Correlation Between Input Voltage and Output CodesVADCnRead codeCorresponding decimal valueVADCm + VREF /GAIN0x1FF511VADCm + 511/512 VREF /GAIN0x1FF511VADCm + 511/512 VREF /GAIN0x1FE510.........VADCm + 1/512 VREF /GAIN0x0011VADCm0x0000VADCm - 1/512 VREF /GAIN0x3FF-1.........VADCm - 511/512 VREF /GAIN0x201-511VADCm - VREF /GAIN0x200-512Example:ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x2702432467M–AVR–11/04ADCL will thus read 0x00, and ADCH will read 0x9C.
Writing zero to ADLAR rightadjusts the result: ADCL = 0x70, ADCH = 0x02.ADC Multiplexer SelectionRegister – ADMUXBit76543210REFS1REFS0ADLARMUX4MUX3MUX2MUX1MUX0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000ADMUX• Bit 7:6 – REFS1:0: Reference Selection BitsThese bits select the voltage reference for the ADC, as shown in Table 97. If these bitsare changed during a conversion, the change will not go in effect until this conversion iscomplete (ADIF in ADCSRA is set). The internal voltage reference options may not beused if an external reference voltage is being applied to the AREF pin.Table 97. Voltage Reference Selections for ADC•REFS1REFS0Voltage Reference Selection00AREF, Internal Vref turned off01AVCC with external capacitor at AREF pin10Reserved11Internal 2.56V Voltage Reference with external capacitor at AREF pinBit 5 – ADLAR: ADC Left Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC DataRegister.
Write one to ADLAR to left adjust the result. Otherwise, the result is rightadjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,regardless of any ongoing conversions. For a complete description of this bit, see “TheADC Data Register – ADCL and ADCH” on page 246.• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to theADC. These bits also select the gain for the differential channels.
See Table 98 fordetails. If these bits are changed during a conversion, the change will not go in effectuntil this conversion is complete (ADIF in ADCSRA is set).Table 98. Input Channel and Gain Selections244MUX4..0Single EndedInput00000ADC000001ADC100010ADC200011ADC300100ADC400101ADC500110ADC600111ADC7Positive DifferentialInputNegative DifferentialInputGainN/A01000ADC0ADC010x01001ADC1ADC010xATmega1282467M–AVR–11/04ATmega128Table 98. Input Channel and Gain Selections (Continued)Positive DifferentialInputNegative DifferentialInputGain01010ADC0ADC0200x01011ADC1ADC0200x01100ADC2ADC210x01101ADC3ADC210x01110ADC2ADC2200x01111ADC3ADC2200x10000ADC0ADC11x10001ADC1ADC11xADC2ADC11x10011ADC3ADC11x10100ADC4ADC11x10101ADC5ADC11x10110ADC6ADC11x10111ADC7ADC11x11000ADC0ADC21x11001ADC1ADC21x11010ADC2ADC21x11011ADC3ADC21x11100ADC4ADC21x11101ADC5ADC21xMUX4..010010ADC Control and StatusRegister A – ADCSRASingle EndedInputN/A111101.23V (VBG)111110V (GND)BitN/A76543210ADENADSCADFRADIFADIEADPS2ADPS1ADPS0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000ADCSRA• Bit 7 – ADEN: ADC EnableWriting this bit to one enables the ADC.
By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.• Bit 6 – ADSC: ADC Start ConversionIn Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion afterADSC has been written after the ADC has been enabled, or if ADSC is written at thesame time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal13. This first conversion performs initialization of the ADC.2452467M–AVR–11/04ADSC will read as one as long as a conversion is in progress.
When the conversion iscomplete, it returns to zero. Writing zero to this bit has no effect.• Bit 5 – ADFR: ADC Free Running SelectWhen this bit is written to one, the ADC operates in Free Running mode. In this mode,the ADC samples and updates the data registers continuously. Writing zero to this bitwill terminate Free Running mode.• Bit 4 – ADIF: ADC Interrupt FlagThis bit is set when an ADC conversion completes and the data registers are updated.The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit inSREG are set.
ADIF is cleared by hardware when executing the corresponding interrupthandling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.Beware that if doing a read-modify-write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.• Bit 3 – ADIE: ADC Interrupt EnableWhen this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.• Bits 2:0 – ADPS2:0: ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the inputclock to the ADC.Table 99. ADC Prescaler SelectionsADPS2ADPS1ADPS0Division Factor0002001201040118100161013211064111128The ADC Data Register –ADCL and ADCHADLAR = 0:BitRead/WriteInitial Value24615141312111098––––––ADC9ADC8ADCHADC7ADC6ADC5ADC4ADC3ADC2ADC1ADC0ADCL76543210RRRRRRRRRRRRRRRR0000000000000000ATmega1282467M–AVR–11/04ATmega128ADLAR = 1:BitRead/WriteInitial Value15141312111098ADC9ADC8ADC7ADC6ADC5ADC4ADC3ADC2ADCHADC1ADC0––––––ADCL76543210RRRRRRRRRRRRRRRR0000000000000000When an ADC conversion is complete, the result is found in these two registers.
If differential channels are used, the result is presented in two’s complement form.When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it issufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result isread from the registers. If ADLAR is set, the result is left adjusted.
If ADLAR is cleared(default), the result is right adjusted.• ADC9:0: ADC Conversion ResultThese bits represent the result from the conversion, as detailed in “ADC ConversionResult” on page 242.2472467M–AVR–11/04JTAG Interface andOn-chip DebugSystemFeatures• JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities According to the IEEE std.
1149.1 (JTAG) Standard• Debugger Access to:– All Internal Peripheral Units– Internal and External RAM– The Internal Register File– Program Counter– EEPROM and Flash Memories• Extensive On-chip Debug Support for Break Conditions, Including– AVR Break Instruction– Break on Change of Program Memory Flow– Single Step Break– Program Memory Breakpoints on Single Address or Address Range– Data Memory Breakpoints on Single Address or Address Range• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface• On-chip Debugging Supported by AVR StudioOverviewThe AVR IEEE std. 1149.1 compliant JTAG interface can be used for•Testing PCBs by using the JTAG Boundary-scan capability•Programming the non-volatile memories, Fuses and Lock bits•On-chip debuggingA brief description is given in the following sections.
Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan Chain can be found in thesections “Programming Via the JTAG Interface” on page 308 and “IEEE 1149.1 (JTAG)Boundary-scan” on page 254, respectively. The On-chip Debug support is consideredbeing private JTAG instructions, and distributed within ATMEL and to selected thirdparty vendors only.Figure 120 shows a block diagram of the JTAG interface and the On-chip Debug system.
The TAP Controller is a state machine controlled by the TCK and TMS signals. TheTAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI – input and TDO – output. TheInstruction Register holds JTAG instructions controlling the behavior of a Data Register.The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registersused for board-level testing. The JTAG Programming Interface (actually consisting ofseveral physical and virtual Data Registers) is used for serial programming via the JTAGinterface.
The Internal Scan Chain and Break Point Scan Chain are used for On-chipdebugging only.Test Access Port – TAP248The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,these pins constitute the Test Access Port –– TAP. These pins are:•TMS: Test mode select. This pin is used for navigating through the TAP-controllerstate machine.•TCK: Test clock.
JTAG operation is synchronous to TCK.•TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or DataRegister (Scan Chains).•TDO: Test Data Out. Serial output data from Instruction Register or Data Register.ATmega1282467M–AVR–11/04ATmega128The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pinsand the TAP controller is in reset.
When programmed and the JTD bit in MCUCSR iscleared, the TAP input signals are internally pulled high and the JTAG is enabled forBoundary-scan and programming. In this case, the TAP output pin (TDO) is left floatingin states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-inputof the next device in the scan chain).
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