ATmega128 (961723), страница 48
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If 200x gain is used, 7-bit resolution can be expected.The ADC contains a Sample and Hold circuit which ensures that the input voltage to theADC is held at a constant level during conversion. A block diagram of the ADC is shownin Figure 108.The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ morethan ± 0.3V from VCC. See the paragraph “ADC Noise Canceler” on page 237 on how toconnect this pin.Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for betternoise performance.2312467M–AVR–11/04Figure 108.
Analog to Digital Converter Block SchematicADC CONVERSIONCOMPLETE IRQ15ADC[9:0]ADPS0ADPS2ADPS1ADIFADFRADENADSC0ADC DATA REGISTER(ADCH/ADCL)ADC CTRL. & STATUSREGISTER (ADCSRA)MUX0MUX2MUX1MUX4MUX3ADLARREFS0REFS1ADC MULTIPLEXERSELECT (ADMUX)ADIEADIF8-BIT DATA BUSPRESCALERAVCCGAIN SELECTIONCHANNEL SELECTIONMUX DECODERCONVERSION LOGICINTERNAL 2.56VREFERENCESAMPLE & HOLDCOMPARATORAREF10-BIT DAC+AGNDBANDGAPREFERENCEADC7SINGLE ENDED / DIFFERENTIAL SELECTIONADC6ADC5ADC MULTIPLEXEROUTPUTPOS.INPUTMUXADC4ADC3+ADC2GAINAMPLIFIERADC1ADC0NEG.INPUTMUX232ATmega1282467M–AVR–11/04ATmega128OperationThe ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation. The minimum value represents GND and the maximum value representsthe voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in theADMUX Register.
The internal voltage reference may thus be decoupled by an externalcapacitor at the AREF pin to improve noise immunity.The analog input channel and differential gain are selected by writing to the MUX bits inADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A selection of ADC input pinscan be selected as positive and negative inputs to the differential gain amplifier.If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. Thisamplified value then becomes the analog input to the ADC.
If single ended channels areused, the gain amplifier is bypassed altogether.The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADCdoes not consume power when ADEN is cleared, so it is recommended to switch off theADC before entering power saving sleep modes.The ADC generates a 10-bit result which is presented in the ADC Data Registers,ADCH and ADCL.
By default, the result is presented right adjusted, but can optionallybe presented left adjusted by setting the ADLAR bit in ADMUX.If the result is left adjusted and no more than 8-bit precision is required, it is sufficient toread ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the contentof the data registers belongs to the same conversion. Once ADCL is read, ADC accessto data registers is blocked. This means that if ADCL has been read, and a conversioncompletes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers isre-enabled.The ADC has its own interrupt which can be triggered when a conversion completes.When ADC access to the data registers is prohibited between reading of ADCH andADCL, the interrupt will trigger even if the result is lost.Starting a ConversionA single conversion is started by writing a logical one to the ADC Start Conversion bit,ADSC.
This bit stays high as long as the conversion is in progress and will be cleared byhardware when the conversion is completed. If a different data channel is selected whilea conversion is in progress, the ADC will finish the current conversion before performingthe channel change.In Free Running mode, the ADC is constantly sampling and updating the ADC DataRegister. Free Running mode is selected by writing the ADFR bit in ADCSRA to one.The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
In this mode the ADC will perform successive conversions independently ofwhether the ADC Interrupt Flag, ADIF is cleared or not.2332467M–AVR–11/04Prescaling andConversion TimingFigure 109. ADC PrescalerADENReset7-BIT ADC PRESCALERCK/64CK/128CK/32CK/8CK/16CK/4CK/2CKADPS0ADPS1ADPS2ADC CLOCK SOURCEBy default, the successive approximation circuitry requires an input clock frequencybetween 50 kHz and 200 kHz to get maximum resolution.
If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get ahigher sample rate.The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bitsin ADCSRA. The prescaler starts counting from the moment the ADC is switched on bysetting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset when ADEN is low.When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle.
See “Differential GainChannels” on page 236 for details on differential conversion timing.A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC isswitched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initializethe analog circuitry.The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normalconversion and 13.5 ADC clock cycles after the start of an first conversion.
When a conversion is complete, the result is written to the ADC data registers, and ADIF is set. Insingle conversion mode, ADSC is cleared simultaneously. The software may then setADSC again, and a new conversion will be initiated on the first rising ADC clock edge.In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, seeTable 95.234ATmega1282467M–AVR–11/04ATmega128Figure 110.
ADC Timing Diagram, First Conversion (Single Conversion Mode)NextConversionFirst ConversionCycle Number121312141615171819202122232425123ADC ClockADENADSCADIFMSB of ResultADCHLSB of ResultADCLMUX and REFSUpdateConversionCompleteSample &HoldMUX and REFSUpdateFigure 111. ADC Timing Diagram, Single ConversionOne ConversionCycle Number12345678Next Conversion109111213123ADC ClockADSCADIFADCHMSB of ResultADCLLSB of ResultSample & HoldMUX and REFSUpdateConversionCompleteMUX and REFSUpdateFigure 112.
ADC Timing Diagram, Free Running ConversionOne ConversionCycle Number1112Next Conversion131234ADC ClockADSCADIFADCHMSB of ResultADCLLSB of ResultConversionCompleteSample & HoldMUX and REFSUpdate2352467M–AVR–11/04Table 95. ADC Conversion TimeConditionConversion Time(Cycles)First conversion14.525Normal conversions, single ended1.5131.5/2.513/14Normal conversions, differentialDifferential Gain ChannelsSample & Hold (Cycles fromStart of Conversion)When using differential gain channels, certain aspects of the conversion need to betaken into consideration.Differential conversions are synchronized to the internal clock CKADC2 equal to half theADC clock.
This synchronization is done automatically by the ADC interface in such away that the sample-and-hold occurs at a specific edge of CKADC2. A conversion initiated by the user (i.e., all single conversions, and the first free running conversion) whenCKADC2 is low will take the same amount of time as a single ended conversion (13 ADCclock cycles from the next prescaled clock cycle). A conversion initiated by the userwhen CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. In free running mode, a new conversion is initiated immediately after the previousconversion completes, and since CKADC2 is high at this time, all automatically started(i.e., all but the first) free running conversions will take 14 ADC clock cycles.The gain stage is optimized for a bandwidth of 4 kHz at all gain settings.
Higher frequencies may be subjected to non-linear amplification. An external low-pass filter should beused if the input signal contains higher frequency components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage bandwidthlimitation. E.g. the ADC clock period may be 6 µs, allowing a channel to be sampled at12 kSPS, regardless of the bandwidth of this channel.Changing Channel orReference SelectionThe MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channelsand reference selection only takes place at a safe point during the conversion. Thechannel and reference selection is continuously updated until a conversion is started.Once the conversion starts, the channel and reference selection is locked to ensure asufficient sampling time for the ADC.
Continuous updating resumes in the last ADCclock cycle before the conversion completes (ADIF in ADCSRA is set). Note that theconversion starts on the following rising ADC clock edge after ADSC is written. The useris thus advised not to write new channel or reference selection values to ADMUX untilone ADC clock cycle after ADSC is written.Special care should be taken when changing differential channels.
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