ATmega128 (961723), страница 51
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The device is shipped with this fuse programmed.For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin ismonitored by the debugger to be able to detect External Reset sources. The debuggercan also pull the RESET pin low to reset the whole system, assuming only open collectors on the Reset line are used in the application.Figure 120. Block DiagramI/O PORT 0DEVICE BOUNDARYBOUNDARY SCAN CHAINTDITDOTCKTMSJTAG PROGRAMMINGINTERFACETAPCONTROLLERAVR CPUBREAKPOINTUNITBYPASSREGISTERPCInstructionFLOW CONTROLUNITDIGITALPERIPHERALUNITSBREAKPOINTSCAN CHAINADDRESSDECODERJTAG / AVR CORECOMMUNICATIONINTERFACEOCD STATUSAND CONTROLAnalog inputsMUXINTERNALSCANCHAINControl & Clock linesIDREGISTERAddressDataANALOGPERIPHERIALUNITSINSTRUCTIONREGISTERFLASHMEMORYI/O PORT n2492467M–AVR–11/04Figure 121. TAP Controller State Diagram1Test-Logic-Reset00Run-Test/Idle1Select-DR Scan1Select-IR Scan0011Capture-DRCapture-IR000Shift-DR11Exit1-DR00Pause-DR0Pause-IR110Exit2-DRExit2-IR11Update-DRTAP Controller1Exit1-IR010Shift-IR101Update-IR010The TAP controller is a 16-state finite state machine that controls the operation of theBoundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
Thestate transitions depicted in Figure 121 depend on the signal present on TMS (shownadjacent to each state transition) at the time of the rising edge at TCK. The initial stateafter a Power-on Reset is Test-Logic-Reset.As a definition in this document, the LSB is shifted in and out first for all Shift Registers.Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:•250At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enterthe Shift Instruction Register – Shift-IR state.
While in this state, shift the 4 bits of theJTAG instructions into the JTAG instruction register from the TDI input at the risingedge of TCK. The TMS input must be held low during input of the 3 LSBs in order toremain in the Shift-IR state. The MSB of the instruction is shifted in when this stateATmega1282467M–AVR–11/04ATmega128is left by setting TMS high.
While the instruction is shifted in from the TDI pin, thecaptured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects aparticular Data Register as path between TDI and TDO and controls the circuitrysurrounding the selected Data Register.•Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instructionis latched onto the parallel output from the Shift Register path in the Update-IRstate.
The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating thestate machine.•At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter theShift Data Register – Shift-DR state. While in this state, upload the selected DataRegister (selected by the present JTAG instruction in the JTAG Instruction Register)from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,the TMS input must be held low during input of all bits except the MSB.
The MSB ofthe data is shifted in when this state is left by setting TMS high. While the DataRegister is shifted in from the TDI pin, the parallel inputs to the Data Registercaptured in the Capture-DR state is shifted out on the TDO pin.•Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selectedData Register has a latched parallel-output, the latching takes place in the UpdateDR state.
The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigatingthe state machine.As shown in the state diagram, the Run-Test/Idle state need not be entered betweenselecting JTAG instruction and using Data Registers, and some JTAG instructions mayselect certain functions to be performed in the Run-Test/Idle, making it unsuitable as anIdle state.Note:Independent of the initial state of the TAP Controller, the Test-Logic-Reset state canalways be entered by holding TMS high for 5 TCK clock periods.For detailed information on the JTAG specification, refer to the literature listed in “Bibliography” on page 253.Using the Boundaryscan ChainA complete description of the Boundary-scan capabilities are given in the section “IEEE1149.1 (JTAG) Boundary-scan” on page 254.Using the On-chip Debug As shown in Figure 120, the hardware support for On-chip Debugging consists mainly ofSystem• A scan chain on the interface between the internal AVR CPU and the internalperipheral units•Break point unit•Communication interface between the CPU and JTAG systemAll read or modify/write operations needed for implementing the Debugger are done byapplying AVR instructions via the internal AVR CPU Scan Chain.
The CPU sends theresult to an I/O memory mapped location which is part of the communication interfacebetween the CPU and the JTAG system.The Break point Unit implements Break on Change of Program Flow, Single Step Break,two Program Memory Breakpoints, and two combined break points. Together, the fourbreak points can be configured as either:•4 single Program Memory break points•3 Single Program Memory break point + 1 single Data Memory break point•2 single Program Memory break points + 2 single Data Memory break points•2 single Program Memory break points + 1 Program Memory break point with mask(“range break point”)2512467M–AVR–11/04•2 single Program Memory break points + 1 Data Memory break point with mask“range break point”.A debugger, like the AVR Studio®, may however use one or more of these resources forits internal purpose, leaving less flexibility to the end-user.A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 252.The JTAGEN fuse must be programmed to enable the JTAG Test Access Port.
In addition, the OCDEN fuse must be programmed and no Lock bits must be set for the Onchip Debug system to work. As a security feature, the On-chip Debug system is disabledwhen any Lock bits are set. Otherwise, the On-chip Debug system would have provideda back-door into a secured device.The AVR Studio enables the user to fully control execution of programs on an AVRdevice with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVRInstruction Set Simulator.
AVR Studio supports source level execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiledwith third party vendors’ compilers.AVR Studio runs under Microsoft® Windows® 95/98/2000 and Windows NT® and Windows XP®.For a full description of the AVR Studio, please refer to the AVR Studio User Guidefound in the Online Help in AVR Studio. Only highlights are presented in this document.All necessary execution commands are available in AVR Studio, both on source leveland on disassembly level.
The user can execute the program, single step through thecode either by tracing into or stepping over functions, step out of functions, place thecursor on a statement and execute until the statement is reached, stop the execution,and reset the execution target. In addition, the user can have an unlimited number ofcode break points (using the BREAK instruction) and up to two data memory breakpoints, alternatively combined as a mask (range) break point.On-chip Debug SpecificJTAG InstructionsThe On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only.
Instruction opcodes arelisted for reference.PRIVATE0; $8Private JTAG instruction for accessing On-chip Debug system.PRIVATE1; $9Private JTAG instruction for accessing On-chip Debug system.PRIVATE2; $APrivate JTAG instruction for accessing On-chip Debug system.PRIVATE3; $BPrivate JTAG instruction for accessing On-chip Debug system.252ATmega1282467M–AVR–11/04ATmega128On-chip Debug RelatedRegister in I/O MemoryOn-chip Debug Register –OCDRBit7654321MSB/IDRD0LSBRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000OCDRThe OCDR Register provides a communication channel from the running program in themicrocontroller to the debugger. The CPU can transfer a byte to the debugger by writingto this location.
At the same time, an internal flag; I/O Debug Register Dirty – IDRD – isset to indicate to the debugger that the register has been written. When the CPU readsthe OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is theIDRD bit. The debugger clears the IDRD bit when it has read the information.In some AVR devices, this register is shared with a standard I/O location. In this case,the OCDR Register can only be accessed if the OCDEN fuse is programmed, and thedebugger enables access to the OCDR Register. In all other cases, the standard I/Olocation is accessed.Refer to the debugger documentation for further information on how to use this register.Using the JTAGProgrammingCapabilitiesProgramming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK,TMS, TDI, and TDO.
These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12Vexternally. The JTAGEN fuse must be programmed and the JTD bit in the MCUCSRRegister must be cleared to enable the JTAG Test Access Port.The JTAG programming capability supports:•Flash programming and verifying•EEPROM programming and verifying•Fuse programming and verifying•Lock bit programming and verifyingThe Lock bit security is exactly as in Parallel Programming mode.
If the Lock bits LB1 orLB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing achip erase. This is a security feature that ensures no back-door exists for reading out thecontent of a secured device.The details on programming through the JTAG interface and programming specificJTAG instructions are given in the section “Programming Via the JTAG Interface” onpage 308.BibliographyFor more information about general Boundary-scan, the following literature can beconsulted:•IEEE: IEEE Std 1149.1-1990.
IEEE Standard Test Access Port and Boundary-scanArchitecture, IEEE, 1993•Colin Maunder: The Board Designers Guide to Testable Logic Circuits, AddisonWesley, 19922532467M–AVR–11/04IEEE 1149.1 (JTAG)Boundary-scanFeatures•••••System OverviewThe Boundary-scan Chain has the capability of driving and observing the logic levels onthe digital I/O pins, as well as the boundary between digital and analog logic for analogcircuitry having off-chip connections. At system level, all ICs having JTAG capabilitiesare connected serially by the TDI/TDO signals to form a long Shift Register. An externalcontroller sets up the devices to drive values at their output pins, and observe the inputvalues received from other devices.
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