ATmega128 (961723), страница 53
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The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn– function, and a bi-directional pin cell that combines the three signals Output Control –OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.The port and pin indexes are not used in the following descriptionThe Boundary-scan logic is not included in the figures in the Data Sheet. Figure 125shows a simple digital Port Pin as described in the section “I/O Ports” on page 63. TheBoundary-scan details from Figure 124 replaces the dashed box in Figure 125.When no alternate port function is present, the Input Data – ID corresponds to the PINxnRegister value (but ID has no synchronizer), Output Data corresponds to the PORTRegister, Output Control corresponds to the Data Direction – DD Register, and the Pullup Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.Digital alternate port functions are connected outside the dotted box in Figure 125 tomake the scan chain read the actual pin value.
For Analog function, there is a directconnection from the external pin to the analog circuit, and a scan chain is inserted onthe interface between the digital logic and the analog circuitry.Figure 124. Boundary-scan Cell for Bi-directional Port Pin with Pull-Up Function.ShiftDRTo Next CellEXTESTPullup Enable (PUE)Vcc0FF2LD210DQDQ1GOutput Control (OC)FF1LD10DQDQ011GOutput Data (OD)01FF0LD00Port Pin (PXn)0DQDQ11GInput Data (ID)From Last Cell258ClockDRUpdateDRATmega1282467M–AVR–11/04ATmega128Figure 125.
General Port Pin Schematic diagramSee Boundary-Scan descriptionfor details!PUExnPUDQDDDxnQ CLRRESETOCxnWDxQPxnODxnDPORTxnQ CLRWPxIDxnDATA BUSRDxRESETRRxSLEEPSYNCHRONIZERDQLQDRPxQPINxnQCLK I/OPUD:PUExn:OCxn:ODxn:IDxn:SLEEP:Boundary-scan and the Twowire InterfacePULLUP DISABLEPULLUP ENABLE for pin PxnOUTPUT CONTROL for pin PxnOUTPUT DATA to pin PxnINPUT DATA from pin PxnSLEEP CONTROLWDx:RDx:WPx:RRx:RPx:CLK I/O :WRITE DDRxREAD DDRxWRITE PORTxREAD PORTx REGISTERREAD PORTx PINI/O CLOCKThe two Two-wire Interface pins SCL and SDA have one additional control signal in thescan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 126, the TWIENsignal enables a tri-state buffer with slew-rate control in parallel with the ordinary digitalport pins.
A general scan cell as shown in Figure 130 is attached to the TWIEN signal.Notes:1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reasonfor having TWIEN in the scan path, is to be able to disconnect the slew-rate controlbuffer when doing boundary-scan.2.
Make sure the OC and TWIEN signals are not asserted simultaneously, as this willlead to drive contention.2592467M–AVR–11/04Figure 126. Additional Scan Signal for the Two-wire InterfacePUExnOCxnODxnTWIENPxnSRCSlew-rate limitedIDxnScanning the RESET PinThe RESET pin accepts 5V active low logic for standard Reset operation, and 12Vactive high logic for High Voltage Parallel programming. An observe-only cell as shownin Figure 127 is inserted both for the 5V Reset signal; RSTT, and the 12V Reset signal;RSTHV.Figure 127. Observe-only CellTonextcellShiftDRTo system logicFrom system pinFF10DQ1FrompreviouscellScanning the Clock PinsClockDRThe AVR devices have many clock options selectable by fuses.
These are: Internal RCOscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator.Figure 128 shows how each Oscillator with external connection is supported in the scanchain. The Enable signal is supported with a general boundary-scan cell, while theOscillator/Clock output is attached to an observe-only cell. In addition to the main clock,the Timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections.260ATmega1282467M–AVR–11/04ATmega128Figure 128.
Boundary-scan Cells for Oscillators and Clock OptionsXTAL1/TOSC1ToNextCellShiftDREXTESTFrom Digital LogicXTAL2/TOSC2Oscillator0ENABLEShiftDRTo System LogicOUTPUT1FF10DQDQ01DGFromPreviousCellClockDRTonextcellQ1UpdateDRFromPreviousCellClockDRTable 102 summaries the scan registers for the external clock pin XTAL1, oscillatorswith XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.Table 102. Scan Signals for the Oscillators(1)(2)(3)Enable signalScanned ClockLineClock OptionScanned Clock Linewhen not UsedEXTCLKENEXTCLK (XTAL1)External Clock0OSCONOSCCKExternal CrystalExternal Ceramic Resonator0RCOSCENRCCKExternal RC1OSC32ENOSC32CKLow Freq.
External Crystal0TOSKONTOSCK32 kHz Timer Oscillator0Notes:Scanning the AnalogComparator1. Do not enable more than one clock source as main clock at a time.2. Scanning an Oscillator output gives unpredictable results as there is a frequency driftbetween the Internal Oscillator and the JTAG TCK clock. If possible, scanning anexternal clock is preferred.3.
The clock configuration is programmed by fuses. As a fuse is not changed run-time,the clock configuration is considered fixed for a given application. The user is advisedto scan the same clock option as to be used in the final system. The enable signalsare supported in the scan chain because the system logic can disable clock optionsin sleep modes, thereby disconnecting the Oscillator pins from the scan path if notprovided. The INTCAP fuses are not supported in the scan-chain, so the boundaryscan chain can not make a XTAL Oscillator requiring internal capacitors to run unlessthe fuse is correctly programmed.The relevant Comparator signals regarding Boundary-scan are shown in Figure 129.The Boundary-scan cell from Figure 130 is attached to each of these signals.
The signals are described in Table 103.The Comparator need not be used for pure connectivity testing, since all analog inputsare shared with a digital port pin as well.2612467M–AVR–11/04Figure 129. Analog comparatorBANDGAPREFERENCEACBGACOAC_IDLEACMEADCENADC MULTIPLEXEROUTPUTFigure 130.
General Boundary-scan Cell used for Signals for Comparator and ADCToNextCellShiftDREXTESTFrom Digital Logic/From Analog Ciruitry01To Analog Circuitry/To Digital Logic0DQDQ1GFromPreviousCell262ClockDRUpdateDRATmega1282467M–AVR–11/04ATmega128Table 103. Boundary-scan Signals for the Analog ComparatorScanning the ADCSignalNameDirection asSeen from theComparatorRecommendedInput when notin UseOutput values whenRecommendedInputs are UsedAC_IDLEInputTurns off Analogcomparator whentrue1Depends upon µCcode being executedACOOutputAnalogComparatorOutputWill becomeinput to µC codebeing executed0ACMEInputUses outputsignal from ADCmux when true0Depends upon µCcode being executedACBGInputBandgapReference enable0Depends upon µCcode being executedDescriptionFigure 131 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 127 is attached to each of these signals.
TheADC need not be used for pure connectivity testing, since all analog inputs are sharedwith a digital port pin as well.Figure 131. Analog to Digital ConverterVCCRENAREFIREFEN2.56VrefTo ComparatorPASSENMUXEN_7ADC_7MUXEN_6ADC_6MUXEN_5ADC_5MUXEN_4ADC_4ADCBGENSCTEST1.22VrefEXTCHMUXEN_3ADC_3MUXEN_2ADC_2MUXEN_1ADC_1MUXEN_0ADC_0PRECHPRECHAREFAREFDACOUTDAC_9..010-bit DAC+COMPG20G10COMP-ADCENACTEN+10xNEGSEL_2-ADC_2NEGSEL_1ADC_020xHOLD-GNDENADC_1NEGSEL_0+STACLKAMPENThe signals are described briefly in Table 104.2632467M–AVR–11/04Table 104.
Boundary-scan Signals for the ADC264SignalNameDirectionas Seenfrom theADCRecommended Inputwhen notin UseOutput Values whenRecommended Inputsare Used, and CPU isnot Using the ADCDescriptionCOMPOutputComparator Output00ACLKInputClock signal to gainstages implementedas Switch-cap filters00ACTENInputEnable path from gainstages to thecomparator00ADCBGENInputEnable Band-gapreference as negativeinput to comparator00ADCENInputPower-on signal to theADC00AMPENInputPower-on signal to thegain stages00DAC_9InputBit 9 of digital value toDAC11DAC_8InputBit 8 of digital value toDAC00DAC_7InputBit 7 of digital value toDAC00DAC_6InputBit 6 of digital value toDAC00DAC_5InputBit 5 of digital value toDAC00DAC_4InputBit 4 of digital value toDAC00DAC_3InputBit 3 of digital value toDAC00DAC_2InputBit 2 of digital value toDAC00DAC_1InputBit 1 of digital value toDAC00DAC_0InputBit 0 of digital value toDAC00EXTCHInputConnect ADCchannels 0 - 3 to bypass path around gainstages11G10InputEnable 10x gain00G20InputEnable 20x gain00ATmega1282467M–AVR–11/04ATmega128Table 104.
Boundary-scan Signals for the ADC (Continued)SignalNameDirectionas Seenfrom theADCGNDENInputGround the negativeinput to comparatorwhen true00HOLDInputSample & Hold signal.Sample analog signalwhen low. Hold signalwhen high. If gainstages are used, thissignal must go activewhen ACLK is high.11IREFENInputEnables Band-gapreference as AREFsignal to DAC00MUXEN_7InputInput Mux bit 700MUXEN_6InputInput Mux bit 600MUXEN_5InputInput Mux bit 500MUXEN_4InputInput Mux bit 400MUXEN_3InputInput Mux bit 300MUXEN_2InputInput Mux bit 200MUXEN_1InputInput Mux bit 100MUXEN_0InputInput Mux bit 011NEGSEL_2InputInput Mux for negativeinput for differentialsignal, bit 200NEGSEL_1InputInput Mux for negativeinput for differentialsignal, bit 100NEGSEL_0InputInput Mux for negativeinput for differentialsignal, bit 000PASSENInputEnable pass-gate ofgain stages.11PRECHInputPrecharge output latchof comparator.
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