ATmega128 (961723), страница 52
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The controller compares the received data with theexpected result. In this way, Boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the four TAPsignals only.JTAG (IEEE std. 1149.1 Compliant) InterfaceBoundary-scan Capabilities According to the JTAG StandardFull Scan of all Port Functions as well as Analog Circuitry having Off-chip ConnectionsSupports the Optional IDCODE InstructionAdditional Public AVR_RESET Instruction to Reset the AVRThe four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instructionAVR_RESET can be used for testing the Printed Circuit Board.
Initial scanning of thedata register path will show the ID-code of the device, since IDCODE is the defaultJTAG instruction. It may be desirable to have the AVR device in reset during Test mode.If not reset, inputs to the device may be determined by the scan operations, and theinternal software may be in an undetermined state when exiting the Test mode. EnteringReset, the outputs of any Port Pin will instantly enter the high impedance state, makingthe HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued tomake the shortest possible scan chain through the device.
The device can be set in theReset state either by pulling the external RESET pin low, or issuing the AVR_RESETinstruction with appropriate setting of the Reset Data Register.The EXTEST instruction is used for sampling external pins and loading output pins withdata. The data from the output latch will be driven out on the pins as soon as theEXTEST instruction is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damagingthe board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOADcan also be used for taking a snapshot of the external pins during normal operation ofthe part.The JTAGEN fuse must be programmed and the JTD bit in the I/O register MCUCSRmust be cleared to enable the JTAG Test Access Port.When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequencyhigher than the internal chip frequency is possible.
The chip clock is not required to run.Data Registers254The data registers relevant for Boundary-scan operations are:•Bypass Register•Device Identification Register•Reset Register•Boundary-scan ChainATmega1282467M–AVR–11/04ATmega128Bypass RegisterThe Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving theCapture-DR controller state. The Bypass Register can be used to shorten the scanchain on a system when the other devices are to be tested.Device Identification RegisterFigure 122 shows the structure of the Device Identification Register.Figure 122. The Format of the Device Identification RegisterLSBMSBBit31Device ID2827121110VersionPart NumberManufacturer ID14 bits16 bits11 bits1-bitVersionVersion is a 4-bit number identifying the revision of the component.
The JTAG versionnumber follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.Part NumberThe part number is a 16-bit code identifying the component. The JTAG Part Number forATmega128 is listed in Table 100.Table 100. AVR JTAG Part NumberPart NumberATmega128Manufacturer IDJTAG Part Number (Hex)0x9702The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in Table 101.Table 101.
Manufacturer IDManufacturerATMELReset RegisterJTAG Manufacturer ID (Hex)0x01FThe Reset Register is a Test Data Register used to reset the part. Since the AVR tristates Port Pins when reset, the Reset Register can also replace the function of theunimplemented optional JTAG instruction HIGHZ.A high value in the Reset Register corresponds to pulling the External Reset low.
Thepart is reset as long as there is a high value present in the Reset Register. Dependingon the Fuse settings for the clock options, the part will remain reset for a Reset TimeOut Period (refer to “Clock Sources” on page 35) after releasing the Reset Register. Theoutput from this Data Register is not latched, so the Reset will take place immediately,as shown in Figure 123.2552467M–AVR–11/04Figure 123.
Reset RegisterToTDOFrom Other Internal andExternal Reset SourcesFromTDIDQInternal ResetClockDR · AVR_RESETBoundary-scan ChainThe Boundary-scan Chain has the capability of driving and observing the logic levels onthe digital I/O pins, as well as the boundary between digital and analog logic for analogcircuitry having off-chip connections.See “Boundary-scan Chain” on page 258 for a complete description.Boundary-scan SpecificJTAG InstructionsThe Instruction Register is 4-bit wide, supporting up to 16 instructions.
Listed below arethe JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZinstruction is not implemented, but all outputs with tri-state capability can be set in highimpedant state by using the AVR_RESET instruction, since the initial state for all portpins is tri-state.As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers.The OPCODE for each instruction is shown behind the instruction name in hex format.The text describes which data register is selected as path between TDI and TDO foreach instruction.EXTEST; $0Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register fortesting circuitry external to the AVR package.
For port-pins, Pull-up Disable, OutputControl, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logicis in the scan chain. The contents of the latched outputs of the Boundary-scan chain isdriven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.The active states are:IDCODE; $1•Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.•Shift-DR: The Internal Scan Chain is shifted by the TCK input.•Update-DR: Data from the scan chain is applied to output pins.Optional JTAG instruction selecting the 32-bit ID Register as Data Register. The ID Register consists of a version number, a device number and the manufacturer code chosenby JEDEC. This is the default instruction after power-up.The active states are:•256Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scanChain.ATmega1282467M–AVR–11/04ATmega128•SAMPLE_PRELOAD; $2Shift-DR: The IDCODE scan chain is shifted by the TCK input.Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot ofthe input/output pins without affecting the system operation.
However, the outputlatched are not connected to the pins. The Boundary-scan Chain is selected as DataRegister.The active states are:AVR_RESET; $C•Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.•Shift-DR: The Boundary-scan Chain is shifted by the TCK input.•Update-DR: Data from the Boundary-scan Chain is applied to the output latches.However, the output latches are not connected to the pins.The AVR specific public JTAG instruction for forcing the AVR device into the Resetmode or releasing the JTAG Reset source. The TAP controller is not reset by thisinstruction. The one bit Reset Register is selected as Data Register.
Note that the Resetwill be active as long as there is a logic 'one' in the Reset Chain. The output from thischain is not latched.The active states are:•BYPASS; $FShift-DR: The Reset Register is shifted by the TCK input.Mandatory JTAG instruction selecting the Bypass Register for Data Register.The active states are:•Capture-DR: Loads a logic “0” into the Bypass Register.•Shift-DR: The Bypass Register cell between TDI and TDO is shifted.Boundary-scan RelatedRegister in I/O MemoryMCU Control and StatusRegister – MCUCSRThe MCU Control and Status Register contains control bits for general MCU functions,and provides information on which reset source caused an MCU Reset.Bit76543210JTD––JTRFWDRFBORFEXTRFPORFRead/WriteR/WRRR/WR/WR/WR/WR/WInitial Value000MCUCSRSee Bit Description• Bit 7 – JTD: JTAG Interface DisableWhen this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed.If this bit is one, the JTAG interface is disabled.
In order to avoid unintentional disablingor enabling of the JTAG interface, a timed sequence must be followed when changingthis bit: The application software must write this bit to the desired value twice within fourcycles to change its value.If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should beset to one. The reason for this is to avoid static current at the TDO pin in the JTAGinterface.• Bit 4 – JTRF: JTAG Reset FlagThis bit is set if a Reset is being caused by a logic one in the JTAG Reset Registerselected by the JTAG instruction AVR_RESET.
This bit is reset by a Power-on Reset, orby writing a logic zero to the flag.2572467M–AVR–11/04Boundary-scan ChainThe Boundary-scan chain has the capability of driving and observing the logic levels onthe digital I/O pins, as well as the boundary between digital and analog logic for analogcircuitry having off-chip connection.Scanning the Digital Port PinsFigure 124 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function.
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