ATmega128 (961723), страница 47
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The following figure showsthe flow in this transfer.Figure 104. Combining Several TWI Modes to Access a Serial EEPROMMaster TransmitterSSLA+WAADDRESSS = STARTTransmitted from master to slaveMaster ReceiverARsSLA+RARs = REPEATED STARTDATAAPP = STOPTransmitted from slave to master2252467M–AVR–11/04Multi-master Systemsand ArbitrationIf multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations arehandled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process.
An example of an arbitration situation isdepicted below, where two masters are trying to transmit data to a slave receiver.Figure 105. An Arbitration ExampleVCCDevice 1Device 2Device 3MASTERTRANSMITTERMASTERTRANSMITTERSLAVERECEIVER........Device nR1R2SDASCLSeveral different scenarios may arise during arbitration, as described below:•Two or more masters are performing identical communication with the same slave.In this case, neither the slave nor any of the masters will know about the buscontention.•Two or more masters are accessing the same slave with different data or directionbit. In this case, arbitration will occur, either in the READ/WRITE bit or in the databits. The masters trying to output a one on SDA while another master outputs a zerowill lose the arbitration. Losing masters will switch to not addressed slave mode orwait until the bus is free and transmit a new START condition, depending onapplication software action.•Two or more masters are accessing different slaves.
In this case, arbitration willoccur in the SLA bits. Masters trying to output a one on SDA while another masteroutputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch toslave mode to check if they are being addressed by the winning master. Ifaddressed, they will switch to SR or ST mode, depending on the value of theREAD/WRITE bit.
If they are not being addressed, they will switch to not addressedslave mode or wait until the bus is free and transmit a new START condition,depending on application software action.This is summarized in Figure 106. Possible status values are given in circles.226ATmega1282467M–AVR–11/04ATmega128Figure 106. Possible Status Codes Caused by ArbitrationSTARTSLADataArbitration lost in SLAOwnAddress / General CallreceivedNoSTOPArbitration lost in Data38TWI bus will be released and not addressed slave mode will be enteredA START condition will be transmitted when the bus becomes freeYesDirectionWrite68/78ReadB0Data byte will be received and NOT ACK will be returnedData byte will be received and ACK will be returnedLast data byte will be transmitted and NOT ACK should be receivedData byte will be transmitted and ACK should be received2272467M–AVR–11/04Analog ComparatorThe Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1.
When the voltage on the positive pin AIN0 is higher than the voltage onthe negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’soutput can be set to trigger the Timer/Counter1 Input Capture function. In addition, thecomparator can trigger a separate interrupt, exclusive to the Analog Comparator. Theuser can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 107.Figure 107.
Analog Comparator Block DiagramBANDGAPREFERENCEACBGACMEADENADC MULTIPLEXER1)OUTPUTNotes:Special Function IO Register –SFIOR1. See Table 94 on page 230.2. Refer to Figure 1 on page 2 and Table 39 on page 78 for Analog Comparator pinplacement.Bit76543210TSM–––ACMEPUDPSR0PSR321Read/WriteR/WRRRR/WR/WR/WR/WInitial Value00000000SFIOR• Bit 3 – ACME: Analog Comparator Multiplexer EnableWhen this bit is written logic one and the ADC is switched off (ADEN in ADCSRA iszero), the ADC multiplexer selects the negative input to the Analog Comparator. Whenthis bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator.
For a detailed description of this bit, see “Analog Comparator Multiplexed Input” onpage 229.Analog Comparator Controland Status Register – ACSRBit76543210ACDACBGACOACIACIEACICACIS1ACIS0Read/WriteR/WR/WRR/WR/WR/WR/WR/WInitial Value00N/A00000ACSR• Bit 7 – ACD: Analog Comparator Disable228ATmega1282467M–AVR–11/04ATmega128When this bit is written logic one, the power to the Analog Comparator is switched off.This bit can be set at any time to turn off the Analog Comparator. This will reduce powerconsumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interruptcan occur when the bit is changed.• Bit 6 – ACBG: Analog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to theAnalog Comparator. When this bit is cleared, AIN0 is applied to the positive input of theAnalog Comparator. See “Internal Voltage Reference” on page 52.• Bit 5 – ACO: Analog Comparator OutputThe output of the Analog Comparator is synchronized and then directly connected toACO. The synchronization introduces a delay of 1 – 2 clock cycles.• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt modedefined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed ifthe ACIE bit is set and the I-bit in SREG is set.
ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing alogic one to the flag.• Bit 3 – ACIE: Analog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.• Bit 2 – ACIC: Analog Comparator Input Capture EnableWhen written logic one, this bit enables the Input Capture function in Timer/Counter1 tobe triggered by the Analog Comparator. The comparator output is in this case directlyconnected to the Input Capture front-end logic, making the comparator utilize the noisecanceler and edge select features of the Timer/Counter1 Input Capture interrupt.
Whenwritten logic zero, no connection between the analog comparator and the Input Capturefunction exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode SelectThese bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in Table 93.Table 93. ACIS1/ACIS0 SettingsACIS1ACIS0Interrupt Mode00Comparator Interrupt on Output Toggle01Reserved10Comparator Interrupt on Falling Output Edge11Comparator Interrupt on Rising Output EdgeWhen changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interruptcan occur when the bits are changed.Analog ComparatorMultiplexed InputIt is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator.
The ADC multiplexer is used to select this input, and consequently, theADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer2292467M–AVR–11/04Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA iszero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 94. If ACME is cleared or ADEN is set, AIN1 isapplied to the negative input to the Analog Comparator.Table 94. Analog Comparator Multiplexed Input230ACMEADENMUX2..0Analog Comparator Negative Input0xxxxAIN111xxxAIN110000ADC010001ADC110010ADC210011ADC310100ADC410101ADC510110ADC610111ADC7ATmega1282467M–AVR–11/04ATmega128Analog to DigitalConverterFeatures••••••••••••••10-bit Resolution0.5 LSB Integral Non-linearity±2 LSB Absolute Accuracy13 - 260 µs Conversion TimeUp to 15 kSPS at Maximum Resolution8 Multiplexed Single Ended Input Channels7 Differential Input Channels2 Differential Input Channels with Optional Gain of 10x and 200xOptional Left Adjustment for ADC Result Readout0 - VCC ADC Input Voltage RangeSelectable 2.56 V ADC Reference VoltageFree Running or Single Conversion ModeInterrupt on ADC Conversion CompleteSleep Mode Noise CancelerThe ATmega128 features a 10-bit successive approximation ADC.
The ADC is connected to an 8-channel Analog Multiplexer which allows 8 single-ended voltage inputsconstructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gainstage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog inputchannels share a common negative terminal (ADC1), while any other ADC input can beselected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can beexpected.
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