ATmega128 (961723), страница 42
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If the value read from the SDA line does not match the value the masterhad output, it has lost the arbitration. Note that a master can only lose arbitration when itoutputs a high SDA value while another master outputs a low value. The losing mastershould immediately go to slave mode, checking if it is being addressed by the winningmaster. The SDA line should be left high, but losing masters are allowed to generate aclock signal until the end of the current data or address packet. Arbitration will continueuntil only one master remains, and this may take many bits. If several masters are tryingto address the same slave, arbitration will continue into the data packet.202ATmega1282467M–AVR–11/04ATmega128Figure 93.
Arbitration Between two MastersSTARTSDA fromMaster AMaster A losesArbitration, SDAA SDASDA fromMaster BSDA LineSynchronizedSCL LineNote that arbitration is not allowed between:•A REPEATED START condition and a data bit•A STOP condition and a data bit•A REPEATED START and a STOP conditionIt is the user software’s responsibility to ensure that these illegal arbitration conditionsnever occur.
This implies that in multi-master systems, all data transfers must use thesame composition of SLA+R/W and data packets. In other words: All transmissionsmust contain the same number of data packets, otherwise the result of the arbitration isundefined.2032467M–AVR–11/04Overview of the TWIModuleThe TWI module is comprised of several submodules, as shown in Figure 94.
All registers drawn in a thick line are accessible through the AVR data bus.Figure 94. Overview of the TWI ModuleSDASpikeFilterSlew-rateControlSpikeFilterBus Interface UnitSTART / STOPControlSpike SuppressionArbitration detectionAddress/Data ShiftRegister (TWDR)Bit Rate GeneratorPrescalerAddress Match UnitAddress Register(TWAR)Bit Rate Register(TWBR)AckControl UnitStatus Register(TWSR)Address ComparatorControl Register(TWCR)State Machine andStatus controlTWI UnitSCLSlew-rateControlScl and SDA PinsThese pins interface the AVR TWI with the rest of the MCU system. The output driverscontain a slew-rate limiter in order to conform to the TWI specification.
The input stagescontain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding tothe SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can insome systems eliminate the need for external ones.Bit Rate Generator UnitThis unit controls the period of SCL when operating in a Master mode. The SCL periodis controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits inthe TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higherthan the SCL frequency.
Note that slaves may prolong the SCL low period, therebyreducing the average TWI bus clock period. The SCL frequency is generated accordingto the following equation:CPU Clock frequencySCL frequency = ---------------------------------------------------------TWPS16 + 2(TWBR) ⋅ 4•TWBR = Value of the TWI Bit Rate Register•TWPS = Value of the prescaler bits in the TWI Status RegisterNote:204TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than10, the master may produce an incorrect output on SDA and SCL for the reminder of thebyte. The problem occurs when operating the TWI in Master mode, sending Start + SLA+ R/W to a slave (a slave does not need to be connected to the bus for the condition tohappen).ATmega1282467M–AVR–11/04ATmega128Bus Interface UnitThis unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware.
The TWDR contains the address or databytes to be transmitted, or the address or data bytes received. In addition to the 8-bitTWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to betransmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating theTWI Control Register (TWCR).
When in Transmitter mode, the value of the received(N)ACK bit can be determined by the value in the TWSR.The START/STOP Controller is responsible for generation and detection of START,REPEATED START, and STOP conditions. The START/STOP controller is able todetect START and STOP conditions even when the AVR MCU is in one of the sleepmodes, enabling the MCU to wake up if addressed by a master.If the TWI has initiated a transmission as master, the Arbitration Detection hardwarecontinuously monitors the transmission trying to determine if arbitration is in process. Ifthe TWI has lost an arbitration, the Control Unit is informed. Correct action can then betaken and appropriate status codes generated.Address Match UnitThe Address Match unit checks if received address bytes match the 7-bit address in theTWI Address Register (TWAR).
If the TWI General Call Recognition Enable (TWGCE)bit in the TWAR is written to one, all incoming address bits will also be comparedagainst the General Call address. Upon an address match, the Control Unit is informed,allowing correct action to be taken. The TWI may or may not acknowledge its address,depending on settings in the TWCR. The Address Match unit is able to compareaddresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up ifaddressed by a master. If another interrupt (e.g., INT0) occurs during TWI Power-downaddress match and wakes up the CPU, the TWI aborts operation and return to it’s idlestate. If this cause any problems, ensure that TWI Address Match is the only enabledinterrupt when entering Power-down.Control UnitThe Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR).
When an event requiring the attention of theapplication occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In thenext clock cycle, the TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWIInterrupt Flag is asserted. At all other times, the TWSR contains a special status codeindicating that no relevant status information is available. As long as the TWINT flag isset, the SCL line is held low. This allows the application software to complete its tasksbefore allowing the TWI transmission to continue.The TWINT flag is set in the following situations:•After the TWI has transmitted a START/REPEATED START condition•After the TWI has transmitted SLA+R/W•After the TWI has transmitted an address byte•After the TWI has lost arbitration•After the TWI has been addressed by own slave address or general call•After the TWI has received a data byte•After a STOP or REPEATED START has been received while still addressed as aslave•When a bus error has occurred due to an illegal START or STOP condition2052467M–AVR–11/04TWI Register DescriptionTWI Bit Rate Register – TWBRBit76543210TWBR7TWBR6TWBR5TWBR4TWBR3TWBR2TWBR1TWBR0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TWBR• Bits 7..0 – TWI Bit Rate RegisterTWBR selects the division factor for the bit rate generator.
The bit rate generator is afrequency divider which generates the SCL clock frequency in the Master modes. See“Bit Rate Generator Unit” on page 204 for calculating bit rates.TWI Control Register – TWCRBit76543210TWINTTWEATWSTATWSTOTWWCTWEN–TWIERead/WriteR/WR/WR/WR/WRR/WRR/WInitial Value00000000TWCRThe TWCR is used to control the operation of the TWI. It is used to enable the TWI, toinitiate a master access by applying a START condition to the bus, to generate areceiver acknowledge, to generate a stop condition, and to control halting of the buswhile the data to be written to the bus are written to the TWDR. It also indicates a writecollision if data is attempted written to TWDR while the register is inaccessible.• Bit 7 – TWINT: TWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current job and expects application software response.
If the I-bit in SREG and TWIE in TWCR are set, the MCU willjump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period isstretched.The TWINT flag must be cleared by software by writing a logic one to it. Note that thisflag is not automatically cleared by hardware when executing the interrupt routine. Alsonote that clearing this flag starts the operation of the TWI, so all accesses to the TWIAddress Register (TWAR), TWI Status Register (TWSR), and TWI Data Register(TWDR) must be complete before clearing this flag.• Bit 6 – TWEA: TWI Enable Acknowledge BitThe TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions aremet:1.
The device’s own slave address has been received.2. A general call has been received, while the TWGCE bit in the TWAR is set.3. A data byte has been received in Master Receiver or Slave Receiver mode.By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily. Address recognition can then be resumed by writing theTWEA bit to one again.• Bit 5 – TWSTA: TWI START Condition BitThe application writes the TWSTA bit to one when it desires to become a master on theTwo-wire Serial Bus. The TWI hardware checks if the bus is available, and generates aSTART condition on the bus if it is free.
However, if the bus is not free, the TWI waitsuntil a STOP condition is detected, and then generates a new START condition to claim206ATmega1282467M–AVR–11/04ATmega128the bus Master status. TWSTA must be cleared by software when the START conditionhas been transmitted.• Bit 4 – TWSTO: TWI STOP Condition BitWriting the TWSTO bit to one in Master mode will generate a STOP condition on theTwo-wire Serial Bus.
When the STOP condition is executed on the bus, the TWSTO bitis cleared automatically. In slave mode, setting the TWSTO bit can be used to recoverfrom an error condition. This will not generate a STOP condition, but the TWI returns toa well-defined unaddressed Slave mode and releases the SCL and SDA lines to a highimpedance state.• Bit 3 – TWWC: TWI Write Collision FlagThe TWWC bit is set when attempting to write to the TWI Data Register – TWDR whenTWINT is low.
This flag is cleared by writing the TWDR Register when TWINT is high.• Bit 2 – TWEN: TWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface. When TWEN iswritten to one, the TWI takes control over the I/O pins connected to the SCL and SDApins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWIis switched off and all TWI transmissions are terminated, regardless of any ongoingoperation.• Bit 1 – Res: Reserved BitThis bit is a reserved bit and will always read as zero.• Bit 0 – TWIE: TWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request willbe activated for as long as the TWINT flag is high.TWI Status Register – TWSRBit76543210TWS7TWS6TWS5TWS4TWS3–TWPS1TWPS0Read/WriteRRRRRRR/WR/WInitial Value11111000TWSR• Bits 7..3 – TWS: TWI StatusThese 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus.
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