ATmega128 (961723), страница 40
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A USART Receive Completeinterrupt will be generated only if the RXCIE bit is written to one, the global interrupt flagin SREG is written to one and the RXC bit in UCSRnA is set.• Bit 6 – TXCIE: TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Completeinterrupt will be generated only if the TXCIEn bit is written to one, the global interruptflag in SREG is written to one and the TXCn bit in UCSRnA is set.• Bit 5 – UDRIEn: USART Data Register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the global interrupt flag inSREG is written to one and the UDREn bit in UCSRnA is set.• Bit 4 – RXENn: Receiver Enable190ATmega1282467M–AVR–11/04ATmega128Writing this bit to one enables the USARTn Receiver.
The Receiver will override normalport operation for the RxDn pin when enabled. Disabling the Receiver will flush thereceive buffer invalidating the FEn, DORn and UPEn flags.• Bit 3 – TXENn: Transmitter EnableWriting this bit to one enables the USARTn Transmitter. The Transmitter will overridenormal port operation for the TxDn pin when enabled. The disabling of the Transmitter(writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and transmit buffer registerdo not contain data to be transmitted. When disabled, the transmitter will no longer override the TxDn port.• Bit 2 – UCSZn2: Character SizeThe UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of databits (character size) in a frame the Receiver and Transmitter use.• Bit 1 – RXB8n: Receive Data Bit 8RXB8n is the ninth data bit of the received character when operating with serial frameswith 9-data bits.
Must be read before reading the low bits from UDRn.• Bit 0 – TXB8n: Transmit Data Bit 8TXB8n is the 9th data bit in the character to be transmitted when operating with serialframes with 9 data bits. Must be written before writing the low bits to UDRn.USART Control and StatusRegister C – UCSRnCBit76543210–UMSELnUPMn1UPMn0USBSnUCSZn1UCSZn0UCPOLnRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000110UCSRnCNote that this register is not available in ATmega103 compatibility mode.• Bit 7 – Reserved BitThis bit is reserved for future use. For compatibility with future devices, these bit must bewritten to zero when UCSRnC is written.• Bit 6 – UMSELn: USART Mode SelectThis bit selects between Asynchronous and Synchronous mode of operation.Table 77.
UMSELn Bit SettingsUMSELnMode0Asynchronous Operation1Synchronous Operation• Bit 5:4 – UPMn1:0: Parity ModeThese bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits withineach frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn flag in UCSRnA will beset.1912467M–AVR–11/04Table 78. UPMn Bits SettingsUPMn1UPMn0Parity Mode00Disabled01(Reserved)10Enabled, Even Parity11Enabled, Odd Parity• Bit 3 – USBSn: Stop Bit SelectThis bit selects the number of stop bits to be inserted by the Transmitter. The Receiverignores this setting.Table 79.
USBSn Bit SettingsUSBSnStop Bit(s)01-bit12-bits• Bit 2:1 – UCSZn1:0: Character SizeThe UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of databits (character size) in a frame the Receiver and Transmitter use.Table 80. UCSZn Bits SettingsUCSZn2UCSZn1UCSZn0Character Size0005-bit0016-bit0107-bit0118-bit100Reserved101Reserved110Reserved1119-bit• Bit 0 – UCPOLn: Clock PolarityThis bit is used for synchronous mode only. Write this bit to zero when Asynchronousmode is used. The UCPOLn bit sets the relationship between data output change anddata input sample, and the synchronous clock (XCKn).Table 81. UCPOLn Bit SettingsTransmitted Data Changed (Output ofTxDn Pin)Received Data Sampled (Input onRxDn Pin)0Rising XCKn EdgeFalling XCKn Edge1Falling XCKn EdgeRising XCKn EdgeUCPOLn192ATmega1282467M–AVR–11/04ATmega128USART Baud Rate Registers –UBRRnL and UBRRnHBit15141312––––111098UBRRn[11:8]UBRRnHUBRRn[7:0]7Read/WriteInitial Value65UBRRnL43210RRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W0000000000000000UBRRnH is not available in mega103 compatibility mode• Bit 15:12 – Reserved BitsThese bits are reserved for future use.
For compatibility with future devices, these bitmust be written to zero when UBRRnH is written.• Bit 11:0 – UBRRn11:0: USARTn Baud Rate RegisterThis is a 12-bit register which contains the USARTn baud rate. The UBRRnH containsthe four most significant bits, and the UBRRnL contains the eight least significant bits ofthe USARTn baud rate.
Ongoing transmissions by the transmitter and receiver will becorrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate updateof the baud rate prescaler.1932467M–AVR–11/04Examples of Baud RateSettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchronous operation can be generated by using the UBRR settings in Table 82.UBRR values which yield an actual baud rate differing less than 0.5% from the targetbaud rate, are bold in the table. Higher error ratings are acceptable, but the receiver willhave less noise resistance when the error ratings are high, especially for large serialframes (see “Asynchronous Operational Range” on page 186). The error values are calculated using the following equation:BaudRate Closest Match- – 1⎞⎠ • 100%Error[%] = ⎛⎝ ------------------------------------------------------BaudRateTable 82.
Examples of UBRR Settings for Commonly Used Oscillator Frequenciesfosc = 1.0000 MHzfosc = 1.8432 MHzfosc = 2.0000 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400250.2%510.2%470.0%950.0%510.2%1030.2%4800120.2%250.2%230.0%470.0%250.2%510.2%96006-7.0%120.2%110.0%230.0%120.2%250.2%14.4k38.5%8-3.5%70.0%150.0%8-3.5%162.1%19.2k28.5%6-7.0%50.0%110.0%6-7.0%120.2%28.8k18.5%38.5%30.0%70.0%38.5%8-3.5%38.4k1-18.6%28.5%20.0%50.0%28.5%6-7.0%57.6k08.5%18.5%10.0%30.0%18.5%38.5%76.8k––1-18.6%1-25.0%20.0%1-18.6%28.5%115.2k––08.5%00.0%10.0%08.5%18.5%230.4k––––––00.0%––––250k––––––––––00.0%Max1.194(1)U2X = 0U2X = 162.5 kbps125 kbpsU2X = 0U2X = 1115.2 kbpsU2X = 0230.4 kbps125 kbpsU2X = 1250 kbpsUBRR = 0, Error = 0.0%ATmega1282467M–AVR–11/04ATmega128Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequenciesfosc = 3.6864 MHzfosc = 4.0000 MHzfosc = 7.3728 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400950.0%1910.0%1030.2%2070.2%1910.0%3830.0%4800470.0%950.0%510.2%1030.2%950.0%1910.0%9600230.0%470.0%250.2%510.2%470.0%950.0%14.4k150.0%310.0%162.1%34-0.8%310.0%630.0%19.2k110.0%230.0%120.2%250.2%230.0%470.0%28.8k70.0%150.0%8-3.5%162.1%150.0%310.0%38.4k50.0%110.0%6-7.0%120.2%110.0%230.0%57.6k30.0%70.0%38.5%8-3.5%70.0%150.0%76.8k20.0%50.0%28.5%6-7.0%50.0%110.0%115.2k10.0%30.0%18.5%38.5%30.0%70.0%230.4k00.0%10.0%08.5%18.5%10.0%30.0%250k0-7.8%1-7.8%00.0%10.0%1-7.8%3-7.8%0.5M––0-7.8%––00.0%0-7.8%1-7.8%1M––––––––––0-7.8%Max1.U2X = 0(1)U2X = 1230.4 kbpsU2X = 0460.8 kbps250 kbpsU2X = 1U2X = 00.5 MbpsU2X = 1460.8 kbps921.6 kbpsUBRR = 0, Error = 0.0%1952467M–AVR–11/04Table 84.
Examples of UBRR Settings for Commonly Used Oscillator Frequenciesfosc = 11.0592 MHzfosc = 8.0000 MHzfosc = 14.7456 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError24002070.2%416-0.1%2870.0%5750.0%3830.0%7670.0%48001030.2%2070.2%1430.0%2870.0%1910.0%3830.0%9600510.2%1030.2%710.0%1430.0%950.0%1910.0%14.4k34-0.8%680.6%470.0%950.0%630.0%1270.0%19.2k250.2%510.2%350.0%710.0%470.0%950.0%28.8k162.1%34-0.8%230.0%470.0%310.0%630.0%38.4k120.2%250.2%170.0%350.0%230.0%470.0%57.6k8-3.5%162.1%110.0%230.0%150.0%310.0%76.8k6-7.0%120.2%80.0%170.0%110.0%230.0%115.2k38.5%8-3.5%50.0%110.0%70.0%150.0%230.4k18.5%38.5%20.0%50.0%30.0%70.0%250k10.0%30.0%2-7.8%5-7.8%3-7.8%65.3%0.5M00.0%10.0%––2-7.8%1-7.8%3-7.8%1M––00.0%––––0-7.8%1-7.8%Max1.196(1)U2X = 0U2X = 10.5 Mbps1 MbpsU2X = 0U2X = 1691.2 kbpsU2X = 01.3824 Mbps921.6 kbpsU2X = 11.8432 MbpsUBRR = 0, Error = 0.0%ATmega1282467M–AVR–11/04ATmega128Table 85.
Examples of UBRR Settings for Commonly Used Oscillator Frequenciesfosc = 16.0000 MHzfosc = 18.4320 MHzfosc = 20.0000 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400416-0.1%8320.0%4790.0%9590.0%5200.0%10410.0%48002070.2%416-0.1%2390.0%4790.0%2590.2%5200.0%96001030.2%2070.2%1190.0%2390.0%1290.2%2590.2%14.4k680.6%138-0.1%790.0%1590.0%86-0.2%173-0.2%19.2k510.2%1030.2%590.0%1190.0%640.2%1290.2%28.8k34-0.8%680.6%390.0%790.0%420.9%86-0.2%38.4k250.2%510.2%290.0%590.0%32-1.4%640.2%57.6k162.1%34-0.8%190.0%390.0%21-1.4%420.9%76.8k120.2%250.2%140.0%290.0%151.7%32-1.4%115.2k8-3.5%162.1%90.0%190.0%10-1.4%21-1.4%230.4k38.5%8-3.5%40.0%90.0%48.5%10-1.4%250k30.0%70.0%4-7.8%82.4%40.0%90.0%0.5M10.0%30.0%––4-7.8%––40.0%1M00.0%10.0%––––––––Max1.U2X = 0(1)1 MbpsU2X = 12 MbpsU2X = 0U2X = 11.152 MbpsU2X = 02.304 MbpsU2X = 11.25 Mbps2.5 MbpsUBRR = 0, Error = 0.0%1972467M–AVR–11/04Two-wire SerialInterfaceFeatures••••••••••Two-wire Serial InterfaceBus DefinitionThe Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications.
The TWI protocol allows the systems designer to interconnect up to 128 differentdevices using only two bi-directional bus lines, one for clock (SCL) and one for data(SDA). The only external hardware needed to implement the bus is a single pull-upresistor for each of the TWI bus lines.
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