ATmega128 (961723), страница 35
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This means that the minimum SCK period willbe 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc /4 or lower.The SPI interface on the ATmega128 is also used for program memory and EEPROMdownloading or uploading. See page 303 for SPI Serial Programming and verification.SPI Data Register – SPDRBit7654321MSB0LSBRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial ValueXXXXXXXXSPDRUndefinedThe SPI Data Register is a Read/Write Register used for data transfer between the register file and the SPI Shift Register. Writing to the register initiates data transmission.Reading the register causes the Shift Register Receive buffer to be read.168ATmega1282467M–AVR–11/04ATmega128Data ModesThere are four combinations of SCK phase and polarity with respect to serial data,which are determined by control bits CPHA and CPOL.
The SPI data transfer formatsare shown in Figure 77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This isclearly seen by summarizing Table 70 and Table 71, as done below:Table 73. CPOL and CPHA FunctionalityLeading edgeTrailing edgeSPI modeCPOL = 0, CPHA = 0Sample (Rising)Setup (Falling)0CPOL = 0, CPHA = 1Setup (Rising)Sample (Falling)1CPOL = 1, CPHA = 0Sample (Falling)Setup (Rising)2CPOL = 1, CPHA = 1Setup (Falling)Sample (Rising)3Figure 77.
SPI Transfer Format with CPHA = 0SCK (CPOL = 0)mode 0SCK (CPOL = 1)mode 2SAMPLE IMOSI/MISOCHANGE 0MOSI PINCHANGE 0MISO PINSSMSB first (DORD = 0)LSB first (DORD = 1)MSBLSBBit 6Bit 1Bit 5Bit 2Bit 4Bit 3Bit 3Bit 4Bit 2Bit 5Bit 1Bit 6LSBMSBFigure 78. SPI Transfer Format with CPHA = 1SCK (CPOL = 0)mode 1SCK (CPOL = 1)mode 3SAMPLE IMOSI/MISOCHANGE 0MOSI PINCHANGE 0MISO PINSSMSB first (DORD = 0)LSB first (DORD = 1)MSBLSBBit 6Bit 1Bit 5Bit 2Bit 4Bit 3Bit 3Bit 4Bit 2Bit 5Bit 1Bit 6LSBMSB1692467M–AVR–11/04USARTThe Universal Synchronous and Asynchronous serial Receiver and Transmitter(USART) is a highly flexible serial communication device.
The main features are:• Full Duplex Operation (Independent Serial Receive and Transmit Registers)• Asynchronous or Synchronous Operation• Master or Slave Clocked Synchronous Operation• High Resolution Baud Rate Generator• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits• Odd or Even Parity Generation and Parity Check Supported by Hardware• Data OverRun Detection• Framing Error Detection• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete• Multi-processor Communication Mode• Double Speed Asynchronous Communication ModeDual USARTThe ATmega128 has two USART’s, USART0 and USART1.
The functionality for bothUSART’s is described below. USART0 and USART1 have different I/O registers asshown in “Register Summary” on page 364. Note that in ATmega103 compatibilitymode, USART1 is not available, neither is the UBRR0H or UCRS0C Registers. Thismeans that in ATmega103 compatibility mode, the ATmega128 supports asynchronousoperation of USART0 only.OverviewA simplified block diagram of the USART transmitter is shown in Figure 79. CPU accessible I/O registers and I/O pins are shown in bold.170ATmega1282467M–AVR–11/04ATmega128Figure 79.
USART Block DiagramClock GeneratorUBRR[H:L]OSCBAUD RATE GENERATORSYNC LOGICPINCONTROLXCKTransmitterTXCONTROLUDR (Transmit)DATABUSPARITYGENERATORTxDReceiverUCSRANote:PINCONTROLTRANSMIT SHIFT REGISTERCLOCKRECOVERYRXCONTROLRECEIVE SHIFT REGISTERDATARECOVERYPINCONTROLUDR (Receive)PARITYCHECKERUCSRBRxDUCSRCRefer to Figure 1 on page 2, Table 36 on page 75, and Table 39 on page 78 for USARTpin placement.The dashed boxes in the block diagram separate the three main parts of the USART(listed from the top): Clock Generator, Transmitter, and Receiver.
Control registers areshared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. TheXCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitterconsists of a single write buffer, a serial Shift Register, parity generator and control logicfor handling different serial frame formats. The write buffer allows a continuous transferof data without any delay between frames.
The Receiver is the most complex part of theUSART module due to its clock and data recovery units. The recovery units are used forasynchronous data reception. In addition to the recovery units, the receiver includes aparity checker, control logic, a Shift Register and a two level receive buffer (UDR). Thereceiver supports the same frame formats as the Transmitter, and can detect frameerror, data overrun and parity errors.1712467M–AVR–11/04AVR USART vs. AVR UART –CompatibilityThe USART is fully compatible with the AVR UART regarding:•Bit locations inside all USART registers•Baud Rate Generation•Transmitter Operation•Transmit Buffer Functionality•Receiver OperationHowever, the receive buffering has two improvements that will affect the compatibility insome special cases:•A second buffer register has been added.
The two buffer registers operate as acircular FIFO buffer. Therefore the UDR must only be read once for each incomingdata! More important is the fact that the error flags (FE and DOR) and the ninth databit (RXB8) are buffered with the data in the receive buffer. Therefore the status bitsmust always be read before the UDR Register is read. Otherwise the error statuswill be lost since the buffer state is lost.•The receiver Shift Register can now act as a third buffer level. This is done byallowing the received data to remain in the serial Shift Register (see Figure 79) if thebuffer registers are full, until a new start bit is detected. The USART is thereforemore resistant to Data OverRun (DOR) error conditions.The following control bits have changed name, but have same functionality and registerlocation:Clock Generation•CHR9 is changed to UCSZ2•OR is changed to DORThe clock generation logic generates the base clock for the transmitter and receiver.The USART supports four modes of clock operation: Normal Asynchronous, DoubleSpeed Asynchronous, Master Synchronous, and Slave Synchronous mode.
TheUMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (Asynchronous mode only) iscontrolled by the U2X found in the UCSRA Register. When using Synchronous mode(UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whetherthe clock source is internal (Master mode) or external (Slave mode). The XCK pin is onlyactive when using Synchronous mode.Figure 80 shows a block diagram of the clock generation logic.Figure 80.
Clock Generation Logic, Block DiagramUBRRU2XfoscPrescalingDown-CounterUBRR+1/2/4/2010OSCDDR_XCKxckiXCKPinDDR_XCKSyncRegisterEdgeDetector10UMSEL1xckoUCPOL10172txclkrxclkATmega1282467M–AVR–11/04ATmega128Signal description:Internal Clock Generation –The Baud Rate GeneratortxclkTransmitter clock. (Internal Signal)rxclkReceiver base clock. (Internal Signal)xckiInput from XCK pin (internal Signal). Used for synchronous slave operation.xckoClock output to XCK pin (Internal Signal). Used for synchronous masteroperation.foscXTAL pin frequency (System Clock).Internal clock generation is used for the asynchronous and the synchronous mastermodes of operation.
The description in this section refers to Figure 80.The USART Baud Rate Register (UBRR) and the down-counter connected to it functionas a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counteddown to zero or when the UBRRL Register is written. A clock is generated each time thecounter reaches zero.
This clock is the baud rate generator clock output (=fosc/(UBRR+1)). The transmitter divides the baud rate generator clock output by 2, 8, or16 depending on mode. The baud rate generator output is used directly by the receiver’sclock and data recovery units. However, the recovery units use a state machine thatuses 2, 8, or 16 states depending on mode set by the state of the UMSEL, U2X andDDR_XCK bits.Table 74 contains equations for calculating the baud rate (in bits per second) and forcalculating the UBRR value for each mode of operation using an internally generatedclock source.Table 74. Equations for Calculating Baud Rate Register SettingEquation for CalculatingBaud Rate(1)Equation for CalculatingUBRR ValueAsynchronous Normal Mode(U2X = 0)f OSCBAUD = -------------------------------------16 ( UBRR + 1 )f OSCUBRR = -----------------------–116BAUDAsynchronous Double SpeedMode (U2X = 1)f OSCBAUD = ---------------------------------8 ( UBRR + 1 )f OSCUBRR = -------------------–18BAUDSynchronous Master Modef OSCBAUD = ---------------------------------2 ( UBRR + 1 )f OSCUBRR = -------------------–12BAUDOperating ModeNote:1.
The baud rate is defined to be the transfer rate in bit per second (bps).BAUD Baud rate (in bits per second, bps)fOSCSystem Oscillator clock frequencyUBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)Some examples of UBRR values for some system clock frequencies are found in Table82 (see page 194).Double Speed Operation(U2X)The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit onlyhas effect for the asynchronous operation. Set this bit to zero when using synchronousoperation.Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectivelydoubling the transfer rate for asynchronous communication. Note however that the1732467M–AVR–11/04receiver will in this case only use half the number of samples (reduced from 16 to 8) fordata sampling and clock recovery, and therefore a more accurate baud rate setting andsystem clock are required when this mode is used. For the Transmitter, there are nodownsides.External ClockExternal clocking is used by the synchronous slave modes of operation.
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