ATmega128 (961723), страница 39
Текст из файла (страница 39)
S = 16 for Normal Speed mode and S = 8 for Double Speedmode.SFFirst sample number used for majority voting. SF = 8 for Normal Speed and SF = 4for Double Speed mode.SMMiddle sample number used for majority voting. SM = 9 for Normal Speed andSM = 5 for Double Speed mode.Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to thereceiver baud rate. R fast is the ratio of the fastest incoming data rate that can beaccepted in relation to the receiver baud rate.Table 75 and Table 76 list the maximum receiver baud rate error that can be tolerated.Note that normal speed mode has higher toleration of baud rate variations.186ATmega1282467M–AVR–11/04ATmega128Table 75.
Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode(U2X = 0)D# (Data+Parity Bit)Rslow %Rfast %Max TotalError %Recommended MaxReceiver Error %593,20106,67+6.67/-6.8± 3.0694,12105,79+5.79/-5.88± 2.5794,81105,11+5.11/-5.19± 2.0895,36104,58+4.58/-4.54± 2.0995,81104,14+4.14/-4.19± 1.51096,17103,78 %+3.78/-3.83± 1.5Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode(U2X = 1)D# (Data+Parity Bit)Rslow %Rfast %Max TotalError %Recommended MaxReceiver Error %594,12105,66+5.66/-5.88± 2.5694,92104,92+4.92/-5.08± 2.0795,52104,35+4.35/-4.48± 1.5896,00103,90+3.90/-4.00± 1.5996,39103,53+3.53/-3.61± 1.51096,70103,23+3.23/-3.30± 1.0The recommendations of the maximum receiver baud rate error was made under theassumption that the receiver and transmitter equally divides the maximum total error.There are two possible sources for the receivers baud rate error.
The receiver’s systemclock (XTAL) will always have some minor instability over the supply voltage range andthe temperature range. When using a crystal to generate the system clock, this is rarelya problem, but for a resonator the system clock may differ more than 2% depending ofthe resonators tolerance. The second source for the error is more controllable. The baudrate generator can not always do an exact division of the system frequency to get thebaud rate wanted. In this case an UBRR value that gives an acceptable low error can beused if possible.Multi-processorCommunication ModeSetting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART receiver. Frames that do notcontain address information will be ignored and not put into the receive buffer. Thiseffectively reduces the number of incoming frames that has to be handled by the CPU,in a system with multiple MCUs that communicate via the same serial bus.
The transmitter is unaffected by the MPCM setting, but has to be used differently when it is a part ofa system utilizing the Multi-processor Communication mode.If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stopbit indicates if the frame contains data or address information. If the receiver is set up forframes with 9 data bits, then the ninth bit (RXB8) is used for identifying address and1872467M–AVR–11/04data frames.
When the frame type bit (the first stop or the 9th bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.The Multi-processor Communication mode enables several slave MCUs to receive datafrom a master MCU. This is done by first decoding an address frame to find out whichMCU has been addressed.
If a particular slave MCU has been addressed, it will receivethe following data frames as normal, while the other slave MCUs will ignore the receivedframes until another address frame is received.Using MPCMFor an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ =7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared whena data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set touse a 9-bit character frame format.The following procedure should be used to exchange data in Multi-processor Communication mode:1.
All slave MCUs are in Multi-processor Communication mode (MPCM in UCSRAis set).2. The master MCU sends an address frame, and all slaves receive and read thisframe. In the slave MCUs, the RXC flag in UCSRA will be set as normal.3. Each slave MCU reads the UDR Register and determines if it has been selected.If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next addressbyte and keeps the MPCM setting.4. The addressed MCU will receive all data frames until a new address frame isreceived. The other slave MCUs, which still have the MPCM bit set, will ignorethe data frames.5. When the last data frame is received by the addressed MCU, the addressedMCU sets the MPCM bit and waits for a new address frame from master.
Theprocess then repeats from 2.Using any of the 5- to 8-bit character frame formats is possible, but impractical since thereceiver must change between using n and n+1 character frame formats. This makesfull-duplex operation difficult since the transmitter and receiver uses the same charactersize setting. If 5- to 8-bit character frames are used, the transmitter must be set to usetwo stop bit (USBS = 1) since the first stop bit is used for indicating the frame type.Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCM bit.The MPCM bit shares the same I/O location as the TXC flag and this might accidentallybe cleared when using SBI or CBI instructions.188ATmega1282467M–AVR–11/04ATmega128USART RegisterDescriptionUSARTn I/O Data Register –UDRnBit76543210RXBn[7:0]UDRn (Read)TXBn[7:0]UDRn (Write)Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share the same I/O address referred to as USARTn Data Register or UDRn.
TheTransmit Data Buffer Register (TXBn) will be the destination for data written to theUDRn Register location. Reading the UDRn Register location will return the contents ofthe receive data buffer register (RXBn).For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitterand set to zero by the Receiver.The transmit buffer can only be written when the UDREn flag in the UCSRAn Register isset.
Data written to UDRn when the UDREn flag is not set, will be ignored by theUSARTn Transmitter. When data is written to the transmit buffer, and the Transmitter isenabled, the Transmitter will load the data into the Transmit Shift Register when theShift Register is empty. Then the data will be serially transmitted on the TxDn pin.The receive buffer consists of a two level FIFO. The FIFO will change its state wheneverthe receive buffer is accessed. Due to this behavior of the receive buffer, do not useread modify write instructions (SBI and CBI) on this location. Be careful when using bittest instructions (SBIC and SBIS), since these also will change the state of the FIFO.USART Control and StatusRegister A – UCSRnABit76543210RXCnTXCnUDREnFEnDORnUPEnU2XnMPCMnRead/WriteRR/WRRRRR/WR/WInitial Value00100000UCSRnA• Bit 7 – RXCn: USART Receive CompleteThis flag bit is set when there are unread data in the receive buffer and cleared when thereceive buffer is empty (i.e., does not contain any unread data).
If the receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will becomezero. The RXCn flag can be used to generate a Receive Complete interrupt (seedescription of the RXCIEn bit).• Bit 6 – TXCn: USART Transmit CompleteThis flag bit is set when the entire frame in the Transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDRn).
TheTXCn flag bit is automatically cleared when a transmit complete interrupt is executed, orit can be cleared by writing a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see description of the TXCIEn bit).• Bit 5 – UDREn: USART Data Register EmptyThe UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. IfUDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flagcan generate a Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready.1892467M–AVR–11/04• Bit 4 – FEn: Frame ErrorThis bit is set if the next character in the receive buffer had a Frame Error whenreceived.
I.e. when the first stop bit of the next character in the receive buffer is zero.This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stopbit of received data is one. Always set this bit to zero when writing to UCSRnA.• Bit 3 – DORn: Data OverRunThis bit is set if a Data OverRun condition is detected. A data overrun occurs when thereceive buffer is full (two characters), it is a new character waiting in the Receive ShiftRegister, and a new start bit is detected. This bit is valid until the receive buffer (UDRn)is read.
Always set this bit to zero when writing to UCSRnA.• Bit 2 – UPEn: Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when receivedand the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until thereceive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.• Bit 1 – U2Xn: Double the USART Transmission SpeedThis bit only has effect for the asynchronous operation. Write this bit to zero when usingsynchronous operation.Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.• Bit 0 – MPCMn: Multi-Processor Communication ModeThis bit enables the Multi-processor Communication mode.
When the MPCMn bit is written to one, all the incoming frames received by the USART Receiver that do not containaddress information will be ignored. The transmitter is unaffected by the MPCMn setting. For more detailed information see “Multi-processor Communication Mode” on page187.USARTn Control and StatusRegister B – UCSRnBBit76543210RXCIEnTXCIEnUDRIEnRXENnTXENnUCSZn2RXB8nTXB8nRead/WriteR/WR/WR/WR/WR/WR/WRR/WInitial Value00000000UCSRnB• Bit 7 – RXCIEn: RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
