ATmega128 (961723), страница 32
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In non-inverting Compare Output mode, the output compare(OC2) is cleared on the compare match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match andcleared at BOTTOM. Due to the single-slope operation, the operating frequency of thefast PWM mode can be twice as high as the phase correct PWM mode that use dualslope operation. This high frequency makes the fast PWM mode well suited for powerregulation, rectification, and DAC applications. High frequency allows physically smallsized external components (coils, capacitors), and therefore reduces total system cost.In fast PWM mode, the counter is incremented until the counter value matches the MAXvalue.
The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 66. The TCNT2 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2slopes represent compare matches between OCR2 and TCNT2.150ATmega1282467M–AVR–11/04ATmega128Figure 66. Fast PWM Mode, Timing DiagramOCRn Interrupt Flag SetOCRn UpdateandTOVn Interrupt Flag SetTCNTnOCn(COMn1:0 = 2)OCn(COMn1:0 = 3)Period1234567The Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If theinterrupt is enabled, the interrupt handler routine can be used for updating the comparevalue.In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2pin.
Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an invertedPWM output can be generated by setting the COM21:0 to 3 (see Table 66 on page 157).The actual OC2 value will only be visible on the port pin if the data direction for the portpin is set as output. The PWM waveform is generated by setting (or clearing) the OC2Register at the compare match between OCR2 and TCNT2, and clearing (or setting) theOC2 Register at the timer clock cycle the counter is cleared (changes from MAX toBOTTOM).The PWM frequency for the output can be calculated by the following equation:f clk_I/Of OCnPWM = ----------------N ⋅ 256The N variable represents the prescale factor (1, 8, 64, 256, or 1024).The extreme values for the OCR2 Register represents special cases when generating aPWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, theoutput will be a narrow spike for each MAX+1 timer clock cycle.
Setting the OCR2 equalto MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC2 to toggle its logical level on each compare match (COM21:0 = 1).
Thewaveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 isset to zero. This feature is similar to the OC2 toggle in CTC mode, except the doublebuffer feature of the output compare unit is enabled in the fast PWM mode.1512467M–AVR–11/04Phase Correct PWM ModeThe phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correctPWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then fromMAX to BOTTOM. In non-inverting Compare Output mode, the output compare (OC2) iscleared on the compare match between TCNT2 and OCR2 while counting up, and seton the compare match while downcounting.
In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications.The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correctPWM mode the counter is incremented until the counter value matches Max When thecounter reaches MAX, it changes the count direction.
The TCNT2 value will be equal toMAX for one timer clock cycle. The timing diagram for the phase correct PWM mode isshown on Figure 67. The TCNT2 value is in the timing diagram shown as a histogramfor illustrating the dual-slope operation. The diagram includes non-inverted and invertedPWM outputs. The small horizontal line marks on the TCNT2 slopes represent comparematches between OCR2 and TCNT2.Figure 67. Phase Correct PWM Mode, Timing DiagramOCn Interrupt Flag SetOCRn UpdateTOVn Interrupt Flag SetTCNTnOCn(COMn1:0 = 2)OCn(COMn1:0 = 3)Period123The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counterreaches the BOTTOM value.In phase correct PWM mode, the compare unit allows generation of PWM waveforms onthe OC2 pin.
Setting the COM21:0 bits to 2 will produce a non-inverted PWM. Aninverted PWM output can be generated by setting the COM21:0 to 3 (see Table 67 onpage 157). The actual OC2 value will only be visible on the port pin if the data directionfor the port pin is set as output. The PWM waveform is generated by clearing (or setting)the OC2 Register at the compare match between OCR2 and TCNT2 when the counterincrements, and setting (or clearing) the OC2 Register at compare match between152ATmega1282467M–AVR–11/04ATmega128OCR2 and TCNT2 when the counter decrements. The PWM frequency for the outputwhen using phase correct PWM can be calculated by the following equation:f clk_I/Of OCnPCPWM = ----------------N ⋅ 510The N variable represents the prescale factor (1, 8, 64, 256, or 1024).The extreme values for the OCR2 Register represent special cases when generating aPWM waveform output in the phase correct PWM mode.
If the OCR2 is set equal toBOTTOM, the output will be continuously low and if set equal to MAX the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.At the very start of Period 2 in Figure 67 OCn has a transition from high to low eventhough there is no Compare Match. The point of this transition is to guarantee symmetryaround BOTTOM. There are two cases that give a transition without a Compare Match:•OCR2A changes its value from MAX, like in Figure 67.
When the OCR2A value isMAX the OCn pin value is the same as the result of a down-counting CompareMatch. To ensure symmetry around BOTTOM the OCn value at MAX mustcorrespond to the result of an up-counting Compare Match.•The timer starts counting from a value higher than the one in OCR2A, and for thatreason misses the Compare Match and hence the OCn change that would havehappened on the way up.1532467M–AVR–11/04Timer/Counter TimingDiagramsThe Timer/Counter is a synchronous design and the timer clock (clkT2) is thereforeshown as a clock enable signal in the following figures.
The figures include informationon when interrupt flags are set. Figure 68 contains timing data for basic Timer/Counteroperation. The figure shows the count sequence close to the MAX value in all modesother than phase correct PWM mode.Figure 68. Timer/Counter Timing Diagram, no PrescalingclkI/OclkTn(clkI/O /1)TCNTnMAX - 1MAXBOTTOMBOTTOM + 1TOVnFigure 69 shows the same timing data, but with the prescaler enabled.Figure 69.
Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnMAX - 1MAXBOTTOMBOTTOM + 1TOVnFigure 70 shows the setting of OCF2 in all modes except CTC mode.154ATmega1282467M–AVR–11/04ATmega128Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnOCRn - 1OCRnOCRnOCRn + 1OCRn + 2OCRn ValueOCFnFigure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, withPrescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTn(CTC)OCRnTOP - 1TOPBOTTOMBOTTOM + 1TOPOCFn1552467M–AVR–11/048-bit Timer/CounterRegister DescriptionTimer/Counter ControlRegister – TCCR2Bit76543210FOC2WGM20COM21COM20WGM21CS22CS21CS20Read/WriteWR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TCCR2• Bit 7 – FOC2: Force Output CompareThe FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode.
However,for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 iswritten when operating in PWM mode. When writing a logical one to the FOC2 bit, animmediate compare match is forced on the waveform generation unit. The OC2 output ischanged according to its COM21:0 bits setting. Note that the FOC2 bit is implementedas a strobe. Therefore it is the value present in the COM21:0 bits that determines theeffect of the forced compare.A FOC2 strobe will not generate any interrupt, nor will it clear the Timer in CTC modeusing OCR2 as TOP.The FOC2 bit is always read as zero.• Bit 6, 3 – WGM21:0: Waveform Generation ModeThese bits control the counting sequence of the counter, the source for the maximum(TOP) counter value, and what type of waveform generation to be used.
Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Comparematch (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table64 and “Modes of Operation” on page 149.Table 64. Waveform Generation Mode Bit DescriptionModeWGM21(CTC2)WGM20(PWM2)Timer/Counter Modeof OperationTOPUpdate ofOCR2 atTOV2 FlagSet on000Normal0xFFImmediateMAX101PWM, Phase Correct0xFFTOPBOTTOM210CTCOCR2ImmediateMAX311Fast PWM0xFFTOPMAXNote:The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
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