ATmega128 (961723), страница 28
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Table 58 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).Table 58. Compare Output Mode, non-PWMCOMnA1/COMnB1/COMnC1COMnA0/COMnB0/COMnC000Normal port operation, OCnA/OCnB/OCnCdisconnected.01Toggle OCnA/OCnB/OCnC on comparematch.10Clear OCnA/OCnB/OCnC on comparematch (set output to low level).11Set OCnA/OCnB/OCnC on compare match(set output to high level).Description1312467M–AVR–11/04Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to thefast PWM modeTable 59. Compare Output Mode, Fast PWMCOMnA1/COMnB1/COMnC0COMnA0/COMnB0/COMnC000Normal port operation, OCnA/OCnB/OCnCdisconnected.01WGMn3:0 = 15: Toggle OCnA on CompareMatch, OCnB/OCnC disconnected (normalport operation).For all other WGMn settings, normal portoperation, OCnA/OCnB/OCnCdisconnected.10Clear OCnA/OCnB/OCnC on comparematch, set OCnA/OCnB/OCnC at TOP11Set OCnA/OCnB/OCnC on compare match,clear OCnA/OCnB/OCnC at TOPNote:DescriptionA special case occurs when OCRnA/OCRnB/OCRnC equals TOP andCOMnA1/COMnB1/COMnC1 is set.
In this case the compare match is ignored, but theset or clear is done at TOP. See “Fast PWM Mode” on page 122. for more details.Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to thephase correct and frequency correct PWM mode.Table 60. Compare Output Mode, Phase Correct and Phase and Frequency CorrectPWMCOMnA1/COMnB/COMnC1COMnA0/COMnB0/COMnC000Normal port operation, OCnA/OCnB/OCnCdisconnected.01WGMn3:0 = 9 or 14: Toggle OCnA onCompare Match, OCnB/OCnC disconnected(normal port operation).For all other WGMn settings, normal portoperation, OCnA/OCnB/OCnCdisconnected.10Clear OCnA/OCnB/OCnC on comparematch when up-counting.
SetOCnA/OCnB/OCnC on compare matchwhen downcounting.11Set OCnA/OCnB/OCnC on compare matchwhen up-counting. ClearOCnA/OCnB/OCnC on compare matchwhen downcounting.Note:132DescriptionA special case occurs when OCRnA/OCRnB/OCRnC equals TOP andCOMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 124. formore details.ATmega1282467M–AVR–11/04ATmega128• Bit 1:0 – WGMn1:0: Waveform Generation ModeCombined with the WGMn3:2 bits found in the TCCRnB Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used, see Table 61.
Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Comparematch (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See“Modes of Operation” on page 121.)Table 61. Waveform Generation Mode Bit DescriptionModeWGMn3WGMn2(CTCn)WGMn1(PWMn1)WGMn0(PWMn0)00000Normal0xFFFFImmediateMAX10001PWM, Phase Correct, 8-bit0x00FFTOPBOTTOM20010PWM, Phase Correct, 9-bit0x01FFTOPBOTTOM30011PWM, Phase Correct, 10-bit0x03FFTOPBOTTOM40100CTCOCRnAImmediateMAX50101Fast PWM, 8-bit0x00FFTOPTOP60110Fast PWM, 9-bit0x01FFTOPTOP70111Fast PWM, 10-bit0x03FFTOPTOP81000PWM, Phase and FrequencyCorrectICRnBOTTOMBOTTOM91001PWM, Phase and FrequencyCorrectOCRnABOTTOMBOTTOM101010PWM, Phase CorrectICRnTOPBOTTOM111011PWM, Phase CorrectOCRnATOPBOTTOM121100CTCICRnImmediateMAX131101(Reserved)–––141110Fast PWMICRnTOPTOP151111Fast PWMOCRnATOPTOPNote:Timer/Counter Mode ofOperation(1)TOPUpdate ofOCRnx atTOVn FlagSet on1.
The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality andlocation of these bits are compatible with previous versions of the timer.1332467M–AVR–11/04Timer/Counter1 ControlRegister B – TCCR1BTimer/Counter3 ControlRegister B – TCCR3BBit76543210ICNC1ICES1–WGM13WGM12CS12CS11CS10Read/WriteR/WR/WRR/WR/WR/WR/WR/WInitial Value00000000Bit76543210ICNC3ICES3–WGM33WGM32CS32CS31CS30Read/WriteR/WR/WRR/WR/WR/WR/WR/WInitial Value00000000TCCR1BTCCR3B• Bit 7 – ICNCn: Input Capture Noise CancelerSetting this bit (to one) activates the Input Capture Noise Canceler.
When the NoiseCanceler is activated, the input from the Input Capture Pin (ICPn) is filtered. The filterfunction requires four successive equal valued samples of the ICPn pin for changing itsoutput. The Input Capture is therefore delayed by four Oscillator cycles when the noisecanceler is enabled.• Bit 6 – ICESn: Input Capture Edge SelectThis bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used astrigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger thecapture.When a capture is triggered according to the ICESn setting, the counter value is copiedinto the Input Capture Register (ICRn).
The event will also set the Input Capture Flag(ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt isenabled.When the ICRn is used as TOP value (see description of the WGMn3:0 bits located inthe TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequentlythe Input Capture function is disabled.• Bit 5 – Reserved BitThis bit is reserved for future use.
For ensuring compatibility with future devices, this bitmust be written to zero when TCCRnB is written.• Bit 4:3 – WGMn3:2: Waveform Generation ModeSee TCCRnA Register description.• Bit 2:0 – CSn2:0: Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter, seeFigure 55 and Figure 56.134ATmega1282467M–AVR–11/04ATmega128Table 62. Clock Select Bit DescriptionCSn2CSn1CSn0Description000No clock source. (Timer/Counter stopped)001clkI/O/1 (No prescaling010clkI/O/8 (From prescaler)011clkI/O/64 (From prescaler)100clkI/O/256 (From prescaler)101clkI/O/1024 (From prescaler)110External clock source on Tn pin.
Clock on falling edge111External clock source on Tn pin. Clock on rising edgeIf external pin modes are used for the Timer/Countern, transitions on the Tn pin willclock the counter even if the pin is configured as an output. This feature allows softwarecontrol of the counting.Timer/Counter1 ControlRegister C – TCCR1CTimer/Counter3 ControlRegister C – TCCR3CBit76543210FOC1AFOC1BFOC1C–––––Read/WriteWWWRRRRRInitial Value00000000Bit76543210FOC3AFOC3BFOC3C–––––Read/WriteWWWRRRRRInitial Value00000000TCCR1CTCCR3C• Bit 7 – FOCnA: Force Output Compare for Channel A• Bit 6 – FOCnB: Force Output Compare for Channel B• Bit 5 – FOCnC: Force Output Compare for Channel CThe FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies anon-PWM mode.
When writing a logical one to the FOCnA/FOCnB/FOCnC bit, animmediate compare match is forced on the waveform generation unit. TheOCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note thatthe FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the valuepresent in the COMnx1:0 bits that determine the effect of the forced compare.A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timerin Clear Timer on Compare Match (CTC) mode using OCRnA as TOP.The FOCnA/FOCnB/FOCnB bits are always read as zero.• Bit 4:0 – Reserved BitsThese bits are reserved for future use.
For ensuring compatibility with future devices,these bits must be written to zero when TCCRnC is written.1352467M–AVR–11/04Timer/Counter1 – TCNT1Hand TCNT1LBit76543210TCNT1[15:8]TCNT1HTCNT1[7:0]Timer/Counter3 – TCNT3Hand TCNT3LTCNT1LRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210TCNT3[15:8]TCNT3HTCNT3[7:0]TCNT3LRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) givedirect access, both for read and for write operations, to the Timer/Counter unit 16-bitcounter. To ensure that both the high and low bytes are read and written simultaneouslywhen the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
This Temporary Register is shared by all the other 16bit registers. See “Accessing 16-bit Registers” on page 112.Modifying the counter (TCNTn) while the counter is running introduces a risk of missinga compare match between TCNTn and one of the OCRnx Registers.Writing to the TCNTn Register blocks (removes) the compare match on the followingtimer clock for all compare units.Output Compare Register 1 A– OCR1AH and OCR1ALBit76543210OCR1A[15:8]OCR1AHOCR1A[7:0]Output Compare Register 1 B– OCR1BH and OCR1BLOCR1ALRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210OCR1B[15:8]OCR1BHOCR1B[7:0]Output Compare Register 1 C– OCR1CH and OCR1CLOCR1BLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210OCR1C[15:8]OCR1CHOCR1C[7:0]Output Compare Register 3 A– OCR3AH and OCR3ALOCR1CLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210OCR3A[15:8]OCR3AHOCR3A[7:0]136OCR3ALRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000ATmega1282467M–AVR–11/04ATmega128Output Compare Register 3 B– OCR3BH and OCR3BLBit76543210OCR3B[15:8]OCR3BHOCR3B[7:0]Output Compare Register 3 C– OCR3CH and OCR3CLOCR3BLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210OCR3C[15:8]OCR3CHOCR3C[7:0]OCR3CLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNTn).
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