ATmega128 (961723), страница 29
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A match can be used to generate an output compareinterrupt, or to generate a waveform output on the OCnx pin.The Output Compare Registers are 16-bit in size. To ensure that both the high and lowbytes are written simultaneously when the CPU writes to these registers, the access isperformed using an 8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page112.Input Capture Register 1 –ICR1H and ICR1LBit76543210ICR1[15:8]ICR1HICR1[7:0]Input Capture Register 3 –ICR3H and ICR3LICR1LRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210ICR3[15:8]ICR3HICR3[7:0]ICR3LRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The Input Capture is updated with the counter (TCNTn) value each time an event occurson the ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1).The Input Capture can be used for defining the counter TOP value.The Input Capture Register is 16-bit in size.
To ensure that both the high and low bytesare read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This Temporary Registeris shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 112.1372467M–AVR–11/04Timer/Counter Interrupt MaskRegister – TIMSKBit76543210OCIE2TOIE2TICIE1OCIE1AOCIE1BTOIE1OCIE0TOIE0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Note:TIMSKThis register contains interrupt control bits for several Timer/Counters, but only Timer1bits are described in this section.
The remaining bits are described in their respectivetimer sections.• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. Thecorresponding interrupt vector (See “Interrupts” on page 57.) is executed when the ICF1flag, located in TIFR, is set.• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match Interrupt is enabled.
Thecorresponding interrupt vector (see “Interrupts” on page 57) is executed when theOCF1A flag, located in TIFR, is set.• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match Interrupt is enabled. Thecorresponding interrupt vector (see “Interrupts” on page 57) is executed when theOCF1B flag, located in TIFR, is set.• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 overflow interrupt is enabled. The correspondinginterrupt vector (see “Interrupts” on page 57) is executed when the TOV1 flag, located inTIFR, is set.Extended Timer/CounterInterrupt Mask Register –ETIMSKBit76543210––TICIE3OCIE3AOCIE3BTOIE3OCIE3COCIE1CRead/WriteRRR/WR/WR/WR/WR/WR/WInitial Value00000000Note:ETIMSKThis register is not available in ATmega103 compatibility mode.• Bit 7:6 – Reserved BitsThese bits are reserved for future use.
For ensuring compatibility with future devices,these bits must be set to zero when ETIMSK is written.• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture Interrupt is enabled. Thecorresponding interrupt vector (see “Interrupts” on page 57) is executed when the ICF3flag, located in ETIFR, is set.• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match Interrupt is enabled.
The138ATmega1282467M–AVR–11/04ATmega128corresponding interrupt vector (see “Interrupts” on page 57) is executed when theOCF3A flag, located in ETIFR, is set.• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match Interrupt is enabled. Thecorresponding interrupt vector (see “Interrupts” on page 57) is executed when theOCF3B flag, located in ETIFR, is set.• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Overflow Interrupt is enabled.
The correspondinginterrupt vector (see “Interrupts” on page 57) is executed when the TOV3 flag, located inETIFR, is set.• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare C Match Interrupt is enabled. Thecorresponding interrupt vector (see “Interrupts” on page 57) is executed when theOCF3C flag, located in ETIFR, is set.• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt EnableWhen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare C Match Interrupt is enabled. Thecorresponding interrupt vector (see “Interrupts” on page 57) is executed when theOCF1C flag, located in ETIFR, is set.Timer/Counter Interrupt FlagRegister – TIFRBit76543210OCF2TOV2ICF1OCF1AOCF1BTOV1OCF0TOV0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Note:TIFRThis register contains flag bits for several Timer/Counters, but only timer 1 bits aredescribed in this section.
The remaining bits are described in their respective timersections.• Bit 5 – ICF1: Timer/Counter1, Input Capture FlagThis flag is set when a capture event occurs on the ICP1 pin. When the Input CaptureRegister (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is setwhen the counter reaches the TOP value.ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match FlagThis flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A).Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.OCF1A is automatically cleared when the Output Compare Match A interrupt vector isexecuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match FlagThis flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B).1392467M–AVR–11/04Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.OCF1B is automatically cleared when the Output Compare Match B interrupt vector isexecuted.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.• Bit 2 – TOV1: Timer/Counter1, Overflow FlagThe setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTCmodes, the TOV1 flag is set when the timer overflows. Refer to Table 61 on page 133for the TOV1 flag behavior when using another WGMn3:0 bit setting.TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector isexecuted.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.Extended Timer/CounterInterrupt Flag Register –ETIFRBit76543210––ICF3OCF3AOCF3BTOV3OCF3COCF1CRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000ETIFR• Bit 7:6 – Reserved BitsThese bits are reserved for future use. For ensuring compatibility with future devices,these bits must be set to zero when ETIFR is written.• Bit 5 – ICF3: Timer/Counter3, Input Capture FlagThis flag is set when a capture event occurs on the ICP3 pin. When the Input CaptureRegister (ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is setwhen the counter reaches the TOP value.ICF3 is automatically cleared when the Input Capture 3 interrupt vector is executed.Alternatively, ICF3 can be cleared by writing a logic one to its bit location.• Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match FlagThis flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register A (OCR3A).Note that a forced output compare (FOC3A) strobe will not set the OCF3A flag.OCF3A is automatically cleared when the Output Compare Match 3 A interrupt vector isexecuted.
Alternatively, OCF3A can be cleared by writing a logic one to its bit location.• Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match FlagThis flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B).Note that a forced output compare (FOC3B) strobe will not set the OCF3B flag.OCF3B is automatically cleared when the Output Compare Match 3 B interrupt vector isexecuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.• Bit 2 – TOV3: Timer/Counter3, Overflow FlagThe setting of this flag is dependent of the WGM3:0 bits setting. In normal and CTCmodes, the TOV3 flag is set when the timer overflows.
Refer to Table 52 on page 102for the TOV3 flag behavior when using another WGM3:0 bit setting.TOV3 is automatically cleared when the Timer/Counter3 Overflow interrupt vector isexecuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.• Bit 1 – OCF3C: Timer/Counter3, Output Compare C Match Flag140ATmega1282467M–AVR–11/04ATmega128This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register C (OCR3C).Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag.OCF3C is automatically cleared when the Output Compare Match 3 C interrupt vector isexecuted.
Alternatively, OCF3C can be cleared by writing a logic one to its bit location.• Bit 0 – OCF1C: Timer/Counter1, Output Compare C Match FlagThis flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C).Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag.OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector isexecuted.
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