ATmega128 (961723), страница 27
Текст из файла (страница 27)
The OCnx interrupt flag will be setwhen a compare match occurs.Figure 53. Phase Correct PWM Mode, Timing DiagramOCRnx / TOP UpdateandOCnA Interrupt Flag Setor ICFn Interrupt Flag Set(Interrupt on TOP)TOVn Interrupt Flag Set(Interrupt on Bottom)TCNTnOCnx(COMnx1:0 = 2)OCnx(COMnx1:0 = 3)Period1234The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA orICFn flag is set accordingly at the same timer clock cycle as the OCRnx Registers areupdated with the double buffer value (at TOP).
The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the compare registers. If the TOP value is lowerthan any of the compare registers, a compare match will never occur between theTCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits aremasked to zero when any of the OCRnx Registers are written.
As the third period shownin Figure 53 illustrates, changing the TOP actively while the Timer/Counter is running inthe phase correct mode can result in an unsymmetrical output. The reason for this canbe found in the time of update of the OCRnx Register. Since the OCRnx update occurs1252467M–AVR–11/04at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope isdetermined by the new TOP value. When these two values differ the two slopes of theperiod will differ in length. The difference in length gives the unsymmetrical result on theoutput.It is recommended to use the phase and frequency correct mode instead of the phasecorrect mode when changing the TOP value while the Timer/Counter is running.
Whenusing a static TOP value there are practically no differences between the two modes ofoperation.In phase correct PWM mode, the compare units allow generation of PWM waveforms onthe OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and aninverted PWM output can be generated by setting the COMnx1:0 to 3 (See Table 60 onpage 132). The actual OCnx value will only be visible on the port pin if the data directionfor the port pin is set as output (DDR_OCnx).
The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTnwhen the counter increments, and clearing (or setting) the OCnx Register at comparematch between OCRnx and TCNTn when the counter decrements. The PWM frequencyfor the output when using phase correct PWM can be calculated by the followingequation:f clk_I/Of OCnxPCPWM = --------------------------2 ⋅ N ⋅ TOPThe N variable represents the prescaler divider (1, 8, 64, 256, or 1024).The extreme values for the OCRnx Register represents special cases when generatinga PWM waveform output in the phase correct PWM mode.
If the OCRnx is set equal toBOTTOM the output will be continuously low and if set equal to TOP the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.If OCnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, theOCnA Output will toggle with a 50% duty cycle.Phase and Frequency CorrectPWM ModeThe phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequencycorrect PWM waveform generation option.
The phase and frequency correct PWMmode is, like the phase correct PWM mode, based on a dual-slope operation. Thecounter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the output compare (OCnx) is cleared onthe compare match between TCNTn and OCRnx while counting up, and set on the compare match while downcounting. In inverting Compare Output mode, the operation isinverted.
The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications.The main difference between the phase correct, and the phase and frequency correctPWM mode is the time the OCRnx Register is updated by the OCRnx buffer Register,(see Figure 53 and Figure 54).The PWM resolution for the phase and frequency correct PWM mode can be defined byeither ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
The PWMresolution in bits can be calculated using the following equation:126ATmega1282467M–AVR–11/04ATmega128log ( TOP + 1 )R PFCPWM = ----------------------------------log ( 2 )In phase and frequency correct PWM mode the counter is incremented until the countervalue matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA(WGMn3:0 = 9).
The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timingdiagram for the phase correct and frequency correct PWM mode is shown on Figure 54.The figure shows phase and frequency correct PWM mode when OCRnA or ICRn isused to define TOP. The TCNTn value is in the timing diagram shown as a histogram forillustrating the dual-slope operation. The diagram includes non-inverted and invertedPWM outputs. The small horizontal line marks on the TCNTn slopes represent comparematches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs.Figure 54.
Phase and Frequency Correct PWM Mode, Timing DiagramOCnA Interrupt Flag Setor ICFn Interrupt Flag Set(Interrupt on TOP)OCRnx / TOP UpdateandTOVn Interrupt Flag Set(Interrupt on Bottom)TCNTnOCnx(COMnx1:0 = 2)OCnx(COMnx1:0 = 3)Period1234The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as theOCRnx Registers are updated with the double buffer value (at BOTTOM). When eitherOCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag set whenTCNTn has reached TOP. The interrupt flags can then be used to generate an interrupteach time the counter reaches the TOP or BOTTOM value.When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the compare registers.
If the TOP value is lowerthan any of the compare registers, a compare match will never occur between theTCNTn and the OCRnx.1272467M–AVR–11/04As Figure 54 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the lengthof the rising and the falling slopes will always be equal. This gives symmetrical outputpulses and is therefore frequency correct.Using the ICRn Register for defining TOP works well when using fixed TOP values. Byusing ICRn, the OCRnA Register is free to be used for generating a PWM output onOCnA. However, if the base PWM frequency is actively changed by changing the TOPvalue, using the OCRnA as TOP is clearly a better choice due to its double bufferfeature.In phase and frequency correct PWM mode, the compare units allow generation ofPWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to 2 will produce a noninverted PWM and an inverted PWM output can be generated by setting the COMnx1:0to 3 (See Table 60 on page 132). The actual OCnx value will only be visible on the portpin if the data direction for the port pin is set as output (DDR_OCnx). The PWMwaveform is generated by setting (or clearing) the OCnx Register at the compare matchbetween OCRnx and TCNTn when the counter increments, and clearing (or setting) theOCnx Register at compare match between OCRnx and TCNTn when the counterdecrements. The PWM frequency for the output when using phase and frequencycorrect PWM can be calculated by the following equation:f clk_I/Of OCnxPFCPWM = --------------------------2 ⋅ N ⋅ TOPThe N variable represents the prescaler divider (1, 8, 64, 256, or 1024).The extreme values for the OCRnx Register represent special cases when generating aPWM waveform output in the phase correct PWM mode.
If the OCRnx is set equal toBOTTOM the output will be continuously low and if set equal to TOP the output will beset to high for non-inverted PWM mode. For inverted PWM the output will have theopposite logic values.If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, theOCnA Output will toggle with a 50% duty cycle.Timer/Counter TimingDiagrams128The Timer/Counter is a synchronous design and the timer clock (clkTn) is thereforeshown as a clock enable signal in the following figures. The figures include informationon when interrupt flags are set, and when the OCRnx Register is updated with theOCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timingdiagram for the setting of OCFnx.ATmega1282467M–AVR–11/04ATmega128Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no PrescalingclkI/OclkTn(clkI/O /1)TCNTnOCRnx - 1OCRnxOCRnxOCRnx + 1OCRnx + 2OCRnx ValueOCFnxFigure 56 shows the same timing data, but with the prescaler enabled.Figure 56.
Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnOCRnxOCRnx - 1OCRnxOCRnx + 1OCRnx + 2OCRnx ValueOCFnxFigure 57 shows the count sequence close to TOP in various modes. When using phaseand frequency correct PWM mode the OCRnx Register is updated at BOTTOM. Thetiming diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 byBOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag atBOTTOM.1292467M–AVR–11/04Figure 57.
Timer/Counter Timing Diagram, no PrescalingclkI/OclkTn(clkI/O /1)TCNTn(CTC and FPWM)TCNTn(PC and PFC PWM)TOP - 1TOPBOTTOMBOTTOM + 1TOP - 1TOPTOP - 1TOP - 2TOVn (FPWM)and ICFn (if usedas TOP)OCRnx(Update at TOP)Old OCRnx ValueNew OCRnx ValueFigure 58 shows the same timing data, but with the prescaler enabled.Figure 58. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTn(CTC and FPWM)TCNTn(PC and PFC PWM)TOP - 1TOPBOTTOMBOTTOM + 1TOP - 1TOPTOP - 1TOP - 2TOVn (FPWM)and ICFn (if usedas TOP)OCRnx(Update at TOP)130Old OCRnx ValueNew OCRnx ValueATmega1282467M–AVR–11/04ATmega12816-bit Timer/CounterRegister DescriptionTimer/Counter1 ControlRegister A – TCCR1ATimer/Counter3 ControlRegister A – TCCR3ABit76543210COM1A1COM1A0COM1B1COM1B0COM1C1COM1C0WGM11WGM10Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210COM3A1COM3A0COM3B1COM3B0COM3C1COM3C0WGM31WGM30Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TCCR1ATCCR3A• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel CThe COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA,OCnB, and OCnC respectively) behavior.
If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it isconnected to. If one or both of the COMnB1:0 bits are written to one, the OCnB outputoverrides the normal port functionality of the I/O pin it is connected to. If one or both ofthe COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register(DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order toenable the output driver.When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0bits is dependent of the WGMn3:0 bits setting.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
