ATmega128 (961723), страница 22
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If the write cycle isnot finished, and the MCU enters sleep mode before the OCR0UB bit returns tozero, the device will never receive a compare match interrupt, and the MCU will notwake up.•If Timer/Counter0 is used to wake the device up from Power-save or ExtendedStandby mode, precautions must be taken if the user wants to re-enter one of thesemodes: The interrupt logic needs one TOSC1 cycle to be reset.
If the time betweenwake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt willnot occur, and the device will fail to wake up. If the user is in doubt whether the timebefore re-entering Power-save or Extended Standby mode is sufficient, the followingalgorithm can be used to ensure that one TOSC1 cycle has elapsed:1. Write a value to TCCR0, TCNT0, or OCR0.2. Wait until the corresponding Update Busy flag in ASSR returns to zero.3. Enter Power-save or Extended Standby mode.•When the asynchronous operation is selected, the 32.768 kHZ Oscillator forTimer/Counter0 is always running, except in Power-down and Standby modes.
Aftera Power-up Reset or wake-up from Power-down or Standby mode, the user shouldbe aware of the fact that this Oscillator might take as long as one second to stabilize.The user is advised to wait for at least one second before using Timer/Counter0after power-up or wake-up from Power-down or Standby mode. The contents of allTimer/Counter0 Registers must be considered lost after a wake-up from Powerdown or Standby mode due to unstable clock signal upon start-up, no matterwhether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.•Description of wake up from Power-save or Extended Standby mode when the timeris clocked asynchronously: When the interrupt condition is met, the wake upprocess is started on the following cycle of the timer clock, that is, the timer isalways advanced by at least one before the processor can read the counter value.After wake-up, the MCU is halted for four cycles, it executes the interrupt routine,and resumes execution from the instruction following SLEEP.•Reading of the TCNT0 Register shortly after wake-up from Power-save may give anincorrect result.
Since TCNT0 is clocked on the asynchronous TOSC clock, readingTCNT0 must be done through a register synchronized to the internal I/O clockdomain. Synchronization takes place for every rising TOSC1 edge. When waking upfrom Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT0 will1052467M–AVR–11/04read as the previous value (before entering sleep) until the next rising TOSC1 edge.The phase of the TOSC clock after waking up from Power-save mode is essentiallyunpredictable, as it depends on the wake-up time.
The recommended procedure forreading TCNT0 is thus as follows:1. Write any value to either of the registers OCR0 or TCCR0.2. Wait for the corresponding Update Busy Flag to be cleared.3. Read TCNT0.•Timer/Counter Interrupt MaskRegister – TIMSKDuring asynchronous operation, the synchronization of the interrupt flags for theasynchronous timer takes three processor cycles plus one timer cycle. The timer istherefore advanced by at least one before the processor can read the timer valuecausing the setting of the interrupt flag.
The output compare pin is changed on thetimer clock and is not synchronized to the processor clock.Bit76543210OCIE2TOIE2TICIE1OCIE1AOCIE1BTOIE1OCIE0TOIE0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TIMSK• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt EnableWhen the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), theTimer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt isexecuted if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set inthe Timer/Counter Interrupt Flag Register – TIFR.• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), theTimer/Counter0 Overflow interrupt is enabled.
The corresponding interrupt is executed ifan overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in theTimer/Counter Interrupt Flag Register – TIFR.Timer/Counter Interrupt FlagRegister – TIFRBit76543210OCF2TOV2ICF1OCF1AOCF1BTOV1OCF0TOV0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TIFR• Bit 1 – OCF0: Output Compare Flag 0The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0and the data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware whenexecuting the corresponding interrupt handling vector.
Alternatively, OCF0 is cleared bywriting a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 CompareMatch Interrupt is executed.• Bit 0 – TOV0: Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is clearedby hardware when executing the corresponding interrupt handling vector. Alternatively,TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), theTimer/Counter0 Overflow Interrupt is executed. In PWM mode, this bit is set whenTimer/Counter0 changes counting direction at $00.106ATmega1282467M–AVR–11/04ATmega128Figure 45.
Prescaler for Timer/Counter0clkT0SPSR0clkT0S/1024clkT0S/128clkT0S/8AS0clkT0S/25610-BIT T/C PRESCALERClearTOSC1clkT0S/64clkI/OclkT0S/32Timer/Counter Prescaler0CS00CS01CS02TIMER/COUNTER0 CLOCK SOURCEclkT0The clock source for Timer/Counter0 is named clkT0. clkT0 is by default connected to themain system clock clkI/O.
By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a RealTime Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected fromPort C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serveas an independent clock source for Timer/Counter0. The Oscillator is optimized for usewith a 32.768 kHz crystal. Applying an external clock source to TOSC1 is notrecommended.For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64,clkT0S/128, clkT0S/256, and clkT0S/1024.
Additionally, clkT0S as well as 0 (stop) may beselected. Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user tooperate with a predictable prescaler.Special Function IO Register –SFIORBit76543210TSM–––ACMEPUDPSR0PSR321Read/WriteR/WRRRR/WR/WR/WR/WInitial Value00000000SFIOR• Bit 7 – TSM: Timer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode.
In thismode, the value that is written to the PSR0 and PSR321 bits is kept, hence keeping thecorresponding prescaler reset signals asserted. This ensures that the correspondingTimer/Counters are halted and can be configured to the same value without the risk ofone of them advancing during configuration. When the TSM bit is written to zero, thePSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start countingsimultaneously.• Bit 1 – PSR0: Prescaler Reset Timer/Counter01072467M–AVR–11/04When this bit is one, the Timer/Counter0 prescaler will be reset.
This bit is normallycleared immediately by hardware. If this bit is written when Timer/Counter0 is operatingin asynchronous mode, the bit will remain one until the prescaler has been reset. The bitwill not be cleared by hardware if the TSM bit is set.108ATmega1282467M–AVR–11/04ATmega12816-bit Timer/Counter(Timer/Counter1 andTimer/Counter3)The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are:• True 16-bit Design (i.e.,Allows 16-bit PWM)• Three Independent Output Compare Units• Double Buffered Output Compare Registers• One Input Capture Unit• Input Capture Noise Canceler• Clear Timer on Compare Match (Auto Reload)• Glitch-free, Phase Correct Pulse width Modulator (PWM)• Variable PWM Period• Frequency Generator• External Event Counter• Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A,OCF3B, OCF3C, and ICF3)Restrictions in ATmega103Compatibility ModeNote that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available(Timer/Counter1).
Also note that in ATmega103 compatibility mode, the Timer/Counter1has two Compare Registers (Compare A and Compare B) only.OverviewMost register and bit references in this section are written in general form. A lower case“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, theprecise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value andso on.A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46.
For theactual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessibleI/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/ORegister and bit locations are listed in the “16-bit Timer/Counter Register Description”on page 131.1092467M–AVR–11/04Figure 46. 16-bit Timer/Counter Block DiagramCountClearDirectionTOVx(Int.Req.)Control LogicTCLKClock SelectEdgeDetectorTOPTxBOTTOM( From Prescaler )Timer/CounterTCNTx==0OCFxA(Int.Req.)WaveformGeneration=OCxAOCRxAOCFxB(Int.Req.)FixedTOPValuesWaveformGenerationDATABUS=OCxBOCRxBOCFxC(Int.Req.)WaveformGeneration=OCRxCOCxC( From AnalogComparator Ouput )ICFx (Int.Req.)EdgeDetectorICRxNoiseCancelerICPxTCCRxANote:RegistersTCCRxBTCCRxCRefer to Figure 1 on page 2, Table 30 on page 71, and Table 39 on page 78 forTimer/Counter1 and 3 pin placement and description.The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register (ICRn) are all 16-bit registers.
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