ATmega128 (961723), страница 17

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Overriding Signals for Alternate Functions PE7..PE4SignalNamePE7/INT7/ICP3PE6/INT6/T3PE5/INT5/OC3CPE4/INT4/OC3BPUOE0000PUOV0000DDOE0000DDOV0000PVOE00OC3C ENABLEOC3B ENABLEPVOV00OC3COC3BDIEOEINT7 ENABLEINT6 ENABLEINT5 ENABLEINT4 ENABLEDIEOV1111DIINT7 INPUT/ICP3INPUTINT7 INPUT/T3INPUTINT5 INPUTINT4 INPUTAIO––––792467M–AVR–11/04Table 41. Overriding Signals for Alternate Functions in PE3..PE0Alternate Functions of Port FSignal NamePE3/AIN1/OC3APE2/AIN0/XCK0PE1/PDO/TXD0PE0/PDI/RXD0PUOE00TXEN0RXEN0PUOV000PORTE0 • PUDDDOE00TXEN0RXEN0DDOV0010PVOEOC3B ENABLEUMSEL0TXEN00PVOVOC3BXCK0 OUTPUTTXD00DIEOE0000DIEOV0000DI0XCK0 INPUT–RXD0AIOAIN1 INPUTAIN0 INPUT––The Port F has an alternate function as analog input for the ADC as shown in Table 42.If some Port F pins are configured as outputs, it is essential that these do not switchwhen a conversion is in progress.

This might corrupt the result of the conversion. InATmega103 compatibility mode Port F is input only. If the JTAG interface is enabled, thepull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if aReset occurs.Table 42. Port F Pins Alternate FunctionsPort PinAlternate FunctionPF7ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)PF6ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)PF5ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)PF4ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)PF3ADC3 (ADC input channel 3)PF2ADC2 (ADC input channel 2)PF1ADC1 (ADC input channel 1)PF0ADC0 (ADC input channel 0)• TDI, ADC7 – Port F, Bit 7ADC7, Analog to Digital Converter, Channel 7.TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register orData Register (scan chains).

When the JTAG interface is enabled, this pin can not beused as an I/O pin.• TDO, ADC6 – Port F, Bit 6ADC6, Analog to Digital Converter, Channel 6.TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.The TDO pin is tri-stated unless TAP states that shift out data are entered.• TMS, ADC5 – Port F, Bit 580ATmega1282467M–AVR–11/04ATmega128ADC5, Analog to Digital Converter, Channel 5.TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controllerstate machine.

When the JTAG interface is enabled, this pin can not be used as an I/Opin.• TCK, ADC4 – Port F, Bit 4ADC4, Analog to Digital Converter, Channel 4.TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.• ADC3 – ADC0 – Port F, Bit 3..0Analog to Digital Converter, Channel 3..0.Table 43. Overriding Signals for Alternate Functions in PF7..PF4SignalNamePF7/ADC7/TDIPF6/ADC6/TDOPF5/ADC5/TMSPF4/ADC4/TCKPUOEJTAGENJTAGENJTAGENJTAGENPUOV1011DDOEJTAGENJTAGENJTAGENJTAGENDDOV0SHIFT_IR +SHIFT_DR00PVOE0JTAGEN00PVOV0TDO00DIEOEJTAGENJTAGENJTAGENJTAGENDIEOV0000DI––––AIOTDI/ADC7 INPUTADC6 INPUTTMS/ADC5INPUTTCKADC4 INPUTTable 44.

Overriding Signals for Alternate Functions in PF3..PF0Signal NamePF3/ADC3PF2/ADC2PF1/ADC1PF0/ADC0PUOE0000PUOV0000DDOE0000DDOV0000PVOE0000PVOV0000DIEOE0000DIEOV0000DI––––AIOADC3 INPUTADC2 INPUTADC1 INPUTADC0 INPUT812467M–AVR–11/04Alternate Functions of Port GIn ATmega103 compatibility mode, only the alternate functions are the defaults for PortG, and Port G cannot be used as General Digital Port Pins.

The alternate pin configuration is as follows:Table 45. Port G Pins Alternate FunctionsPort PinAlternate FunctionPG4TOSC1 (RTC Oscillator Timer/Counter0)PG3TOSC2 (RTC Oscillator Timer/Counter0)PG2ALE (Address Latch Enable to external memory)PG1RD (Read strobe to external memory)PG0WR (Write strobe to external memory)• TOSC1 – Port G, Bit 4TOSC2, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, andbecomes the input of the inverting Oscillator amplifier.

In this mode, a Crystal Oscillatoris connected to this pin, and the pin can not be used as an I/O pin.• TOSC2 – Port G, Bit 3TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, andbecomes the inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillatoris connected to this pin, and the pin can not be used as an I/O pin.• ALE – Port G, Bit 2ALE is the external data memory Address Latch Enable signal.• RD – Port G, Bit 1RD is the external data memory read control strobe.• WR – Port G, Bit 0WR is the external data memory write control strobe.Table 46 and Table 47 relates the alternate functions of Port G to the overriding signalsshown in Figure 33 on page 68.Table 46.

Overriding Signals for Alternate Functions in PG4..PG182Signal NamePG4/TOSC1PG3/TOSC2PG2/ALEPG1/RDPUOEAS0AS0SRESREPUOV0000DDOEAS0AS0SRESREDDOV0011PVOE00SRESREPVOV00ALERDDIEOEAS0AS000DIEOV0000DI––––AIOT/C0 OSC INPUTT/C0 OSC OUTPUT––ATmega1282467M–AVR–11/04ATmega128Table 47. Overriding Signals for Alternate Functions in PG0Signal NamePG0/WRPUOESREPUOV0DDOESREDDOV1PVOESREPVOVWRDIEOE0DIEOV0DI–AIO–832467M–AVR–11/04Register Description forI/O PortsPort A Data Register – PORTABitPort A Data Direction Register– DDRAPort A Input Pins Address –PINA76543210PORTA7PORTA6PORTA5PORTA4PORTA3PORTA2PORTA1PORTA0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDA7DDA6DDA5DDA4DDA3DDA2DDA1DDA0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit7PINA7Read/WriteRInitial ValueN/A6543210PINA6PINA5PINA4PINA3PINA2PINA1PINA0RRRRRRRN/AN/AN/AN/AN/AN/AN/APORTADDRAPINAPort B Data Register – PORTBBitPort B Data Direction Register– DDRBPort B Input Pins Address –PINB76543210PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APORTBDDRBPINBPort C Data Register – PORTCBitPort C Data Direction Register– DDRC8476543210PORTC7PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDC7DDC6DDC5DDC4DDC3DDC2DDC1DDC0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000PORTCDDRCATmega1282467M–AVR–11/04ATmega128Port C Input Pins Address –PINCBit76543210PINC7PINC6PINC5PINC4PINC3PINC2PINC1PINC0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APINCIn ATmega103 compatibility mode, DDRC and PINC Registers are initialized to beingPush-Pull Zero Output.

The port pins assumes their initial value, even if the clock is notrunning. Note that the DDRC and PINC Registers are available in ATmega103 compatibility mode, and should not be used for 100% back-ward compatibility.Port D Data Register – PORTDBitPort D Data Direction Register– DDRDPort D Input Pins Address –PIND76543210PORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APORTDDDRDPINDPort E Data Register – PORTEBitPort E Data Direction Register– DDREPort E Input Pins Address –PINE76543210PORTE7PORTE6PORTE5PORTE4PORTE3PORTE2PORTE1PORTE0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDE7DDE6DDE5DDE4DDE3DDE2DDE1DDE0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PINE7PINE6PINE5PINE4PINE3PINE2PINE1PINE0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APORTEDDREPINFPort F Data Register – PORTFBit76543210PORTF7PORTF6PORTF5PORTF4PORTF3PORTF2PORTF1PORTF0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000PORTF852467M–AVR–11/04Port F Data Direction Register– DDRFPort F Input Pins Address –PINFBit76543210DDF7DDF6DDF5DDF4DDF3DDF2DDF1DDF0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PINF7PINF6PINF5PINF4PINF3PINF2PINF1PINF0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/ADDRFPINFNote that PORTF and DDRF Registers are not available in ATmega103 compatibilitymode where Port F serves as digital input only.Port G Data Register – PORTGBitPort G Data Direction Register– DDRGPort G Input Pins Address –PING76543210–––PORTG4PORTG3PORTG2PORTG1PORTG0Read/WriteRRRR/WR/WR/WR/WR/WInitial Value00000000Bit76543210–––DDG4DDG3DDG2DDG1DDG0Read/WriteRRRR/WR/WR/WR/WR/WInitial Value00000000Bit76543210–––PING4PING3PING2PING1PING0Read/WriteRRRRRRRRInitial Value000N/AN/AN/AN/AN/APORTGDDRGPINGNote that PORTG, DDRG, and PING are not available in ATmega103 compatibilitymode.

In the ATmega103 compatibility mode Port G serves its alternate functions only(TOSC1, TOSC2, WR, RD and ALE).86ATmega1282467M–AVR–11/04ATmega128External InterruptsThe External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, theinterrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggeredby a falling or rising edge or a low level. This is set up as indicated in the specification forthe External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4).

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