ATmega128 (961723), страница 16
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SPI MSTR INPUT and SPI SLAVE OUTPUT constitutethe MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVEINPUT.72ATmega1282467M–AVR–11/04ATmega128Table 31. Overriding Signals for Alternate Functions in PB7..PB4Signal NamePB7/OC2/OC1CPB6/OC1BPB5/OC1APB4/OC0PUOE0000PUOV0000DDOE0000DDOV0000(1)PVOEOC2/OC1C ENABLEOC1B ENABLEOC1A ENABLEOC0 ENABLEPVOVOC2/OC1C(1)OC1BOC1AOC0BDIEOE0000DIEOV0000DI––––AIO––––Note:1.
See “Output Compare Modulator (OCM1C2)” on page 160 for details. OC1C doesnot exist in ATmega103 compatibility mode.Table 32. Overriding Signals for Alternate Functions in PB3..PB0SignalNamePB3/MISOPB2/MOSIPB1/SCKPB0/SSPUOESPE • MSTRSPE • MSTRSPE • MSTRSPE • MSTRPUOVPORTB3 • PUDPORTB2 • PUDPORTB1 • PUDPORTB0 • PUDDDOESPE • MSTRSPE • MSTRSPE • MSTRSPE • MSTRDDOV0000PVOESPE • MSTRSPE • MSTRSPE • MSTR0PVOVSPI SLAVE OUTPUTSPI MSTR OUTPUTSCK OUTPUT0DIEOE0000DIEOV0000DISPI MSTR INPUTSPI SLAVE INPUTSCK INPUTSPI SSAIO––––732467M–AVR–11/04Alternate Functions of Port CIn ATmega103 compatibility mode, Port C is output only. The ATmega128 is by defaultshipped in compatibility mode. Thus, if the parts are not programmed before they areput on the PCB, PORTC will be output during first power up, and until the ATmega103compatibility mode is disabled.
The Port C has an alternate function as the address highbyte for the External Memory Interface.Table 33. Port C Pins Alternate FunctionsPort PinAlternate FunctionPC7A15PC6A14PC5A13PC4A12PC3A11PC2A10PC1A9PC0A8Table 34 and Table 35 relate the alternate functions of Port C to the overriding signalsshown in Figure 33 on page 68.Table 34. Overriding Signals for Alternate Functions in PC7..PC4SignalName(1)PC6/A14PC5/A13PC4/A12PUOESRE • (XMM <1)SRE • (XMM<2)SRE • (XMM<3)SRE • (XMM<4)PUOV0000DDOESRE • (XMM<1)SRE • (XMM<2)SRE • (XMM<3)SRE • (XMM<4)DDOV1111PVOESRE • (XMM<1)SRE • (XMM<2)SRE • (XMM<3)SRE • (XMM<4)PVOVA11A10A9A8DIEOE0000DIEOV0000DI––––AIO––––Note:74PC7/A151.
XMM = 0 in ATmega103 compatibility mode.ATmega1282467M–AVR–11/04ATmega128Table 35. Overriding Signals for Alternate Functions in PC3..PC0(1)SignalNamePC3/A11PC2/A10PC1/A9PC0/A8PUOESRE • (XMM<5)SRE • (XMM<6)SRE • (XMM<7)SRE • (XMM<7)PUOV0000DDOESRE • (XMM<5)SRE • (XMM<6)SRE • (XMM<7)SRE • (XMM<7)DDOV1111PVOESRE • (XMM<5)SRE • (XMM<6)SRE • (XMM<7)SRE • (XMM<7)PVOVA11A10A9A8DIEOE0000DIEOV0000DI––––AIO––––Note:Alternate Functions of Port D1.
XMM = 0 in ATmega103 compatibility mode.The Port D pins with alternate functions are shown in Table 36.Table 36. Port D Pins Alternate FunctionsPort PinAlternate FunctionPD7T2 (Timer/Counter2 Clock Input)PD6T1 (Timer/Counter1 Clock Input)PD5XCK1(1) (USART1 External Clock Input/Output)PD4ICP1 (Timer/Counter1 Input Capture Pin)PD3INT3/TXD1(1) (External Interrupt3 Input or UART1 Transmit Pin)PD2INT2/RXD1(1) (External Interrupt2 Input or UART1 Receive Pin)PD1INT1/SDA(1) (External Interrupt1 Input or TWI Serial DAta)PD0INT0/SCL(1) (External Interrupt0 Input or TWI Serial CLock)Note:1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibilitymode.The alternate pin configuration is as follows:• T2 – Port D, Bit 7T2, Timer/Counter2 counter source.• T1 – Port D, Bit 6T1, Timer/Counter1 counter source.• XCK1 – Port D, Bit 4XCK1, USART1 External clock.
The Data Direction Register (DDD4) controls whetherthe clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active onlywhen the USART1 operates in Synchronous mode.752467M–AVR–11/04• ICP1 – Port D, Bit 4ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin forTimer/Counter1.• INT3/TXD1 – Port D, Bit 3INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt sourceto the MCU.TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitteris enabled, this pin is configured as an output regardless of the value of DDD3.• INT2/RXD1 – Port D, Bit 2INT2, External Interrupt source 2.
The PD2 pin can serve as an External Interruptsource to the MCU.RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver isenabled this pin is configured as an input regardless of the value of DDD2. When theUSART forces this pin to be an input, the pull-up can still be controlled by the PORTD2bit.• INT1/SDA – Port D, Bit 1INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt sourceto the MCU.SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) toenable the Two-wire Serial Interface, pin PD1 is disconnected from the port andbecomes the Serial Data I/O pin for the Two-wire Serial Interface.
In this mode, there isa spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and thepin is driven by an open drain driver with slew-rate limitation.• INT0/SCL – Port D, Bit 0INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt sourceto the MCU.SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) toenable the Two-wire Serial Interface, pin PD0 is disconnected from the port andbecomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there isa spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and thepin is driven by an open drain driver with slew-rate limitation.Table 37 and Table 38 relates the alternate functions of Port D to the overriding signalsshown in Figure 33 on page 68.76ATmega1282467M–AVR–11/04ATmega128Table 37.
Overriding Signals for Alternate Functions PD7..PD4Signal NamePD7/T2PD6/T1PD5/XCK1PD4/ICP1PUOE0000PUOV0000DDOE0000DDOV0000PVOE00UMSEL10PVOV00XCK1 OUTPUT0DIEOE0000DIEOV0000DIT2 INPUTT1 INPUTXCK1 INPUTICP1 INPUTAIO––––Table 38. Overriding Signals for Alternate Functions in PD3..PD0(1)Signal NamePD3/INT3/TXD1PD2/INT2/RXD1PD1/INT1/SDAPD0/INT0/SCLPUOETXEN1RXEN1TWENTWENPUOV0PORTD2 • PUDPORTD1 • PUDPORTD0 • PUDDDOETXEN1RXEN1TWENTWENDDOV10SDA_OUTSCL_OUTPVOETXEN10TWENTWENPVOVTXD1000DIEOEINT3 ENABLEINT2 ENABLEINT1 ENABLEINT0 ENABLEDIEOV1111DIINT3 INPUTINT2 INPUT/RXD1INT1 INPUTINT0 INPUTAIO––SDA INPUTSCL INPUTNote:1.
When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters areconnected between the AIO outputs shown in the port figure and the digital logic ofthe TWI module.772467M–AVR–11/04Alternate Functions of Port EThe Port E pins with alternate functions are shown in Table 39.Table 39. Port E Pins Alternate FunctionsPort PinAlternate FunctionPE7INT7/ICP3(1) (External Interrupt 7 Input or Timer/Counter3 Input Capture Pin)PE6INT6/ T3(1) (External Interrupt 6 Input or Timer/Counter3 Clock Input)PE5INT5/OC3C(1) (External Interrupt 5 Input or Output Compare and PWM Output Cfor Timer/Counter3)PE4INT4/OC3B(1) (External Interrupt4 Input or Output Compare and PWM Output B forTimer/Counter3)PE3AIN1/OC3A (1) (Analog Comparator Negative Input or Output Compare and PWMOutput A for Timer/Counter3)PE2AIN0/XCK0(1) (Analog Comparator Positive Input or USART0 external clockinput/output)PE1PDO/TXD0 (Programming Data Output or UART0 Transmit Pin)PE0PDI/RXD0 (Programming Data Input or UART0 Receive Pin)Note:1.
ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 compatibility mode.• INT7/ICP3 – Port E, Bit 7INT7, External Interrupt source 7: The PE7 pin can serve as an external interruptsource.ICP3 – Input Capture Pin3: The PE7 pin can act as an Input Capture Pin forTimer/Counter3.• INT6/T3 – Port E, Bit 6INT6, External Interrupt source 6: The PE6 pin can serve as an external interruptsource.T3, Timer/Counter3 counter source.• INT5/OC3C – Port E, Bit 5INT5, External Interrupt source 5: The PE5 pin can serve as an External Interruptsource.OC3C, Output Compare Match C output: The PE5 pin can serve as an External outputfor the Timer/Counter3 Output Compare C. The pin has to be configured as an output(DDE5 set “one”) to serve this function. The OC3C pin is also the output pin for thePWM mode timer function.• INT4/OC3B – Port E, Bit 4INT4, External Interrupt source 4: The PE4 pin can serve as an External Interruptsource.OC3B, Output Compare Match B output: The PE4 pin can serve as an External outputfor the Timer/Counter3 Output Compare B.
The pin has to be configured as an output(DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWMmode timer function.• AIN1/OC3A – Port E, Bit 3AIN1 – Analog Comparator Negative input. This pin is directly connected to the negativeinput of the Analog Comparator.78ATmega1282467M–AVR–11/04ATmega128OC3A, Output Compare Match A output: The PE3 pin can serve as an External outputfor the Timer/Counter3 Output Compare A. The pin has to be configured as an output(DDE3 set “one”) to serve this function.
The OC3A pin is also the output pin for the PWMmode timer function.• AIN0/XCK0 – Port E, Bit 2AIN0 – Analog Comparator Positive input. This pin is directly connected to the positiveinput of the Analog Comparator.XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whetherthe clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active onlywhen the USART0 operates in Synchronous mode.• PDO/TXD0 – Port E, Bit 1PDO, SPI Serial Programming Data Output.
During Serial Program Downloading, thispin is used as data output line for the ATmega128.TXD0, UART0 Transmit pin.• PDI/RXD0 – Port E, Bit 0PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pinis used as data input line for the ATmega128.RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When theUSART0 receiver is enabled this pin is configured as an input regardless of the value ofDDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 willturn on the internal pull-up.Table 40 and Table 41 relates the alternate functions of Port E to the overriding signalsshown in Figure 33 on page 68.Table 40.
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