ATmega128 (961723), страница 12
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To save power, the reference is not always turnedon. The reference is on during the following situations:1. When the BOD is enabled (by programming the BODEN fuse).2. When the bandgap reference is connected to the Analog Comparator (by settingthe ACBG bit in ACSR).3. When the ADC is enabled.Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, theuser must always allow the reference to start up before the output from the Analog Comparator or ADC is used.
To reduce power consumption in Power-down mode, the usercan avoid the three conditions above to ensure that the reference is turned off beforeentering Power-down mode.Table 20. Internal Voltage Reference CharacteristicsSymbolWatchdog TimerParameterMinTypMaxUnitsVBGBandgap reference voltage1.151.231.40VtBGBandgap reference start-up time4070µsIBGBandgap reference current consumption10µAThe Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz.This is the typical value at VCC = 5V. See characterization data for typical values at otherVCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset intervalcan be adjusted as shown in Table 22 on page 54. The WDR – Watchdog Reset –instruction resets the Watchdog Timer.
The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selectedto determine the reset period. If the reset period expires without another WatchdogReset, the ATmega128 resets and executes from the Reset Vector. For timing details onthe Watchdog Reset, refer to page 51.To prevent unintentional disabling of the Watchdog or unintentional change of time-outperiod, 3 different safety levels are selected by the Fuses M103C and WDTON asshown in Table 21.
Safety level 0 corresponds to the setting in ATmega103. There is norestriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequencesfor Changing the Configuration of the Watchdog Timer” on page 55 for details.52ATmega1282467M–AVR–11/04ATmega128Table 21. WDT Configuration as a Function of the Fuse Settings of M103C andWDTON.SafetyLevelWDT InitialStateHow to Disablethe WDTHow toChangeTime-outM103CWDTONUnprogrammedUnprogrammed1DisabledTimedsequenceTimedsequenceUnprogrammedProgrammed2EnabledAlways enabledTimedsequenceProgrammedUnprogrammed0DisabledTimedsequenceNorestrictionProgrammedProgrammed2EnabledAlways enabledTimedsequenceFigure 28. Watchdog TimerWATCHDOGOSCILLATORWatchdog Timer ControlRegister – WDTCRBit76543210–––WDCEWDEWDP2WDP1WDP0Read/WriteRRRR/WR/WR/WR/WR/WInitial Value00000000WDTCR• Bits 7..5 – Res: Reserved BitsThese bits are reserved bits in the ATmega128 and will always read as zero.• Bit 4 – WDCE: Watchdog Change EnableThis bit must be set when the WDE bit is written to logic zero.
Otherwise, the Watchdogwill not be disabled. Once written to one, hardware will clear this bit after four clockcycles. Refer to the description of the WDE bit for a Watchdog disable procedure. InSafety Level 1 and 2, this bit must also be set when changing the prescaler bits. See“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 55.• Bit 3 – WDE: Watchdog EnableWhen the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE iswritten to logic zero, the Watchdog Timer function is disabled. WDE can only be clearedif the WDCE bit has logic level one.
To disable an enabled Watchdog Timer, the following procedure must be followed:532467M–AVR–11/041. In the same operation, write a logic one to WDCE and WDE. A logic one must bewritten to WDE even though it is set to one before the disable operation starts.2. Within the next four clock cycles, write a logic 0 to WDE.
This disables theWatchdog.In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of theWatchdog Timer” on page 55.• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when theWatchdog Timer is enabled. The different prescaling values and their correspondingTimeout Periods are shown in Table 22.Table 22. Watchdog Timer Prescale Select54WDP2WDP1WDP0Number of WDTOscillator CyclesTypical Time-outat VCC = 3.0VTypical Time-outat VCC = 5.0V00016K (16,384)14.8 ms14.0 ms00132K (32,768)29.6 ms28.1 ms01064K (65,536)59.1 ms56.2 ms011128K (131,072)0.12 s0.11 s100256K (262,144)0.24 s0.22 s101512K (524,288)0.47 s0.45 s1101,024K (1,048,576)0.95 s0.9 s1112,048K (2,097,152)1.9 s1.8 sATmega1282467M–AVR–11/04ATmega128The following code example shows one assembly and one C function for turning off theWDT.
The example assumes that interrupts are controlled (e.g. by disabling interruptsglobally) so that no interrupts will occur during execution of these functions.Assembly Code ExampleWDT_off:; Reset WDTwdrin r16, WDTCR; Write logical one to WDCE and WDEori r16, (1<<WDCE)|(1<<WDE)out WDTCR, r16; Turn off WDTldi r16, (0<<WDE)out WDTCR, r16retC Code Examplevoid WDT_off(void){/* Reset WDT*/__watchdog_reset();/* Write logical one to WDCE and WDE */WDTCR |= (1<<WDCE) | (1<<WDE);/* Turn off WDT */WDTCR = 0x00;}Timed Sequences for Changing the Configuration of the Watchdog TimerThe sequence for changing configuration differs slightly between the three safety levels.Separate procedures are described for each level.Safety Level 0This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 withoutany restriction.
The time-out period can be changed at any time without restriction. Todisable an enabled Watchdog Timer, the procedure described on page 53 (WDE bitdescription) must be followed.Safety Level 1In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing theWDE bit to 1 without any restriction. A timed sequence is needed when changing theWatchdog Time-out period or disabling an enabled Watchdog Timer. To disable anenabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed:1.
In the same operation, write a logic one to WDCE and WDE. A logic one must bewritten to WDE regardless of the previous value of the WDE bit.2. Within the next four clock cycles, in the same operation, write the WDE and WDPbits as desired, but with the WDCE bit cleared.552467M–AVR–11/04Safety Level 2In this mode, the Watchdog Timer is always enabled, and the WDE bit will always readas one. A timed sequence is needed when changing the Watchdog Time-out period. Tochange the Watchdog Time-out, the following procedure must be followed:1. In the same operation, write a logical one to WDCE and WDE.
Even though theWDE always is set, the WDE must be written to one to start the timed sequence.2. Within the next four clock cycles, in the same operation, write the WDP bits asdesired, but with the WDCE bit cleared. The value written to the WDE bit isirrelevant.56ATmega1282467M–AVR–11/04ATmega128InterruptsInterrupt Vectors inATmega128This section describes the specifics of the interrupt handling as performed inATmega128. For a general explanation of the AVR interrupt handling, refer to “Resetand Interrupt Handling” on page 13.Table 23. Reset and Interrupt VectorsVectorNo.ProgramAddress(2)SourceInterrupt Definition1$0000(1)RESETExternal Pin, Power-on Reset, Brown-out Reset,Watchdog Reset, and JTAG AVR Reset2$0002INT0External Interrupt Request 03$0004INT1External Interrupt Request 14$0006INT2External Interrupt Request 25$0008INT3External Interrupt Request 36$000AINT4External Interrupt Request 47$000CINT5External Interrupt Request 58$000EINT6External Interrupt Request 69$0010INT7External Interrupt Request 710$0012TIMER2 COMPTimer/Counter2 Compare Match11$0014TIMER2 OVFTimer/Counter2 Overflow12$0016TIMER1 CAPTTimer/Counter1 Capture Event13$0018TIMER1 COMPATimer/Counter1 Compare Match A14$001ATIMER1 COMPBTimer/Counter1 Compare Match B15$001CTIMER1 OVFTimer/Counter1 Overflow16$001ETIMER0 COMPTimer/Counter0 Compare Match17$0020TIMER0 OVFTimer/Counter0 Overflow18$0022SPI, STCSPI Serial Transfer Complete19$0024USART0, RXUSART0, Rx Complete20$0026USART0, UDREUSART0 Data Register Empty21$0028USART0, TXUSART0, Tx Complete22$002AADCADC Conversion Complete23$002CEE READYEEPROM Ready24$002EANALOG COMPAnalog Comparator25$0030(3)TIMER1 COMPCTimer/Countre1 Compare Match C26(3)TIMER3 CAPTTimer/Counter3 Capture Event(3)TIMER3 COMPATimer/Counter3 Compare Match A28(3)$0036TIMER3 COMPBTimer/Counter3 Compare Match B29$0038(3)TIMER3 COMPCTimer/Counter3 Compare Match C30(3)TIMER3 OVFTimer/Counter3 Overflow27$0032$0034$003A572467M–AVR–11/04Table 23.
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