ATmega128 (961723), страница 8
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Since the External MemoryAddress bit A15 is not connected to the external memory, addresses 0x8000 to 0x90FFwill appear as addresses 0x0000 to 0x10FF for the external memory. Addressing aboveaddress 0x90FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software,the external 32 KB memory will appear as one linear 32 KB address space from 0x1100to 0x90FF. This is illustrated in Figure 17. Memory configuration B refers to theATmega103 compatibility mode, configuration A to the non-compatible mode.312467M–AVR–11/04When the device is set in ATmega103 compatibility mode, the internal address space is4,096 bytes.
This implies that the first 4,096 bytes of the external memory can beaccessed at addresses 0x8000 to 0x8FFF. To the Application software, the external 32KB memory will appear as one linear 32 KB address space from 0x1000 to 0x8FFF.Figure 17. Address Map with 32 KB External MemoryMemory Configuration BMemory Configuration AAVR Memory Map0x0000External 32K SRAMAVR Memory Map0x0000Internal Memory0x10FF0x11000x7FFF0x80000x10FF0x1100ExternalMemory0x90FF0x91000x7FFF0x00000x0FFF0x10000x7FFF0x8000320x0000Internal MemoryExternal0x0FFF0x10000x7FFFMemory0x8FFF0x9000(Unused)0xFFFFExternal 32K SRAM(Unused)0xFFFFATmega1282467M–AVR–11/04ATmega128Using all 64KB Locations ofExternal MemorySince the External Memory is mapped after the Internal Memory as shown in Figure 11,only 60KB of External Memory is available by default (address space 0x0000 to 0x10FFis reserved for internal memory).
However, it is possible to take advantage of the entireExternal Memory by masking the higher address bits to zero. This can be done by usingthe XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releasing the most significant bits for normal Port Pinoperation, the Memory Interface will address 0x0000 - 0x1FFF. See the following codeexamples.Assembly Code Example(1);;;;;OFFSET is defined to 0x2000 to ensureexternal memory accessConfigure Port C (address high byte) tooutput 0x00 when the pins are releasedfor normal Port Pin operationldi r16, 0xFFout DDRC, r16ldi r16, 0x00out PORTC, r16; release PC7:5ldi r16, (1<<XMM1)|(1<<XMM0)sts XMCRB, r16; write 0xAA to address 0x0001 of external; memoryldi r16, 0xaasts 0x0001+OFFSET, r16; re-enable PC7:5 for external memoryldi r16, (0<<XMM1)|(0<<XMM0)sts XMCRB, r16; store 0x55 to address (OFFSET + 1) of; external memoryldi r16, 0x55sts 0x0001+OFFSET, r16C Code Example(1)#define OFFSET 0x2000void XRAM_example(void){unsigned char *p = (unsigned char *) (OFFSET + 1);DDRC = 0xFF;PORTC = 0x00;XMCRB = (1<<XMM1) | (1<<XMM0);*p = 0xaa;XMCRB = 0x00;*p = 0x55;}Note:1.
The example code assumes that the part specific header file is included.Care must be exercised using this option as most of the memory is masked away.332467M–AVR–11/04System Clock andClock OptionsClock Systems and theirDistributionFigure 18 presents the principal clock systems in the AVR and their distribution.
All ofthe clocks need not be active at a given time. In order to reduce power consumption, theclocks to modules not being used can be halted by using different sleep modes, asdescribed in “Power Management and Sleep Modes” on page 42. The clock systemsare detailed below.Figure 18. Clock DistributionAsynchronousTimer/CounterGeneral I/OmodulesADCCPU CoreRAMFlash andEEPROMclkADCclkI/OclkCPUAVR ClockControl UnitclkASYclkFLASHReset LogicSource clockWatchdog clockClockMultiplexerTimer/CounterOscillatorExternal RCOscillatorExternal clockWatchdog TimerWatchdogOscillatorCrystalOscillatorLow-FrequencyCrystal OscillatorCalibrated RCOscillatorCPU Clock – clkCPUThe CPU clock is routed to parts of the system concerned with operation of the AVRcore.
Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits thecore from performing general operations and calculations.I/O Clock – clkI/OThe I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, andUSART. The I/O clock is also used by the External Interrupt module, but note that someexternal interrupts are detected by asynchronous logic, allowing such interrupts to bedetected even if the I/O clock is halted. Also note that address recognition in the TWImodule is carried out asynchronously when clkI/O is halted, enabling TWI address reception in all sleep modes.Flash Clock – clkFLASHThe Flash clock controls operation of the Flash interface.
The Flash clock is usuallyactive simultaneously with the CPU clock.34ATmega1282467M–AVR–11/04ATmega128Asynchronous Timer Clock –clkASYThe Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clockeddirectly from an external 32 kHz clock crystal. The dedicated clock domain allows usingthis Timer/Counter as a real-time counter even when the device is in sleep mode.ADC Clock – clkADCThe ADC is provided with a dedicated clock domain. This allows halting the CPU andI/O clocks in order to reduce noise generated by digital circuitry.
This gives more accurate ADC conversion results.Clock SourcesThe device has the following clock source options, selectable by Flash fuse bits asshown below. The clock from the selected source is input to the AVR clock generator,and routed to the appropriate modules.Table 6. Device Clocking Options SelectDevice Clocking OptionCKSEL3..0(1)External Crystal/Ceramic Resonator1111 - 1010External Low-frequency Crystal1001External RC Oscillator1000 - 0101Calibrated Internal RC Oscillator0100 - 0001External ClockNote:00001. For all fuses “1” means unprogrammed while “0” means programmed.The various choices for each clocking option is given in the following sections.
When theCPU wakes up from Power-down or Power-save, the selected clock source is used totime the start-up, ensuring stable Oscillator operation before instruction execution starts.When the CPU starts from reset, there is as an additional delay allowing the power toreach a stable level before commencing normal operation. The Watchdog Oscillator isused for timing this real-time part of the start-up time. The number of WDT Oscillatorcycles used for each time-out is shown in Table 7.
The frequency of the Watchdog Oscillator is voltage dependent as shown in the “ATmega128 Typical Characteristics” onpage 335.Table 7. Number of Watchdog Oscillator CyclesDefault Clock SourceTypical Time-out (VCC = 5.0V)Typical Time-Out (VCC = 3.0V)Number of Cycles4.1 ms4.3 ms4K (4,096)65 ms69 ms64K (65,536)The device is shipped with CKSEL = “0001” and SUT = “10”.
The default clock sourcesetting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an InSystem or Parallel Programmer.352467M–AVR–11/04Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured for use as an On-chip Oscillator, as shown in Figure 19.
Either a quartzcrystal or a ceramic resonator may be used. The CKOPT fuse selects between two different Oscillator Amplifier modes. When CKOPT is programmed, the Oscillator outputwill oscillate will a full rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clockbuffer. This mode has a wide frequency range. When CKOPT is unprogrammed, theOscillator has a smaller output swing. This reduces power consumption considerably.This mode has a limited frequency range and it can not be used to drive other clockbuffers.For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16MHz with CKOPT programmed.
C1 and C2 should always be equal for both crystals andresonators. The optimal value of the capacitors depends on the crystal or resonator inuse, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given inTable 8. For ceramic resonators, the capacitor values given by the manufacturer shouldbe used.Figure 19.
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