ATmega128 (961723), страница 3
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In addition, theATmega128 has Extended I/O space from $60 - $FF in SRAM where only theST/STS/STD and LD/LDS/LDD instructions can be used.ALU – Arithmetic LogicUnitThe high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, arithmetic operations betweengeneral purpose registers or between a register and an immediate are executed. TheALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.Status RegisterThe Status Register contains information about the result of the most recently executedarithmetic instruction.
This information can be used for altering program flow in order toperform conditional operations. Note that the Status Register is updated after all ALUoperations, as specified in the Instruction Set Reference. This will in many casesremove the need for using the dedicated compare instructions, resulting in faster andmore compact code.The status register is not automatically stored when entering an interrupt routine andrestored when returning from an interrupt.
This must be handled by software.The AVR status Register – SREG – is defined as:Bit76543210ITHSVNZCRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000SREG• Bit 7 – I: Global Interrupt Enable92467M–AVR–11/04The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the GlobalInterrupt Enable Register is cleared, none of the interrupts are enabled independent ofthe individual interrupt enable settings. The I-bit is cleared by hardware after an interrupthas occurred, and is set by the RETI instruction to enable subsequent interrupts.
The Ibit can also be set and cleared in software with the SEI and CLI instructions, asdescribed in the instruction set reference.• Bit 6 – T: Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source ordestination for the operated bit. A bit from a register in the Register file can be copiedinto T by the BST instruction, and a bit in T can be copied into a bit in a register in theRegister file by the BLD instruction.• Bit 5 – H: Half Carry FlagThe Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry isuseful in BCD arithmetic.
See the “Instruction Set Description” for detailed information.• Bit 4 – S: Sign Bit, S = N⊕VThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the “Instruction Set Description” for detailed information.• Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetics. Seethe “Instruction Set Description” for detailed information.• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. Seethe “Instruction Set Description” for detailed information.• Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.• Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation.
See the “Instruction Set Description” for detailed information.General PurposeRegister FileThe Register file is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output schemes aresupported by the Register file:•One 8-bit output operand and one 8-bit result input•Two 8-bit output operands and one 8-bit result input•Two 8-bit output operands and one 16-bit result input•One 16-bit output operand and one 16-bit result inputFigure 4 shows the structure of the 32 general purpose working registers in the CPU.Figure 4. AVR CPU General Purpose Working Registers7100Addr.R0$00R1$01R2$02ATmega1282467M–AVR–11/04ATmega128…R13$0DGeneralR14$0EPurposeR15$0FWorkingR16$10RegistersR17$11…R26$1AX-register Low ByteR27$1BX-register High ByteR28$1CY-register Low ByteR29$1DY-register High ByteR30$1EZ-register Low ByteR31$1FZ-register High ByteMost of the instructions operating on the Register file have direct access to all registers,and most of them are single cycle instructions.As shown in Figure 4, each register is also assigned a data memory address, mappingthem directly into the first 32 locations of the user Data Space.
Although not being physically implemented as SRAM locations, this memory organization provides greatflexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set toindex any register in the file.X-register, Y-register, and ZregisterThe registers R26..R31 have some added functions to their general purpose usage.These registers are 16-bit address pointers for indirect addressing of the Data Space.The three indirect address registers X, Y, and Z are described in Figure 5.Figure 5.
The X-, Y-, and Z-registers15X - registerXH7XL0R27 ($1B)15Y - registerYH7157R31 ($1F)00R26 ($1A)YL0R29 ($1D)Z - register7700R28 ($1C)ZHZL0700R30 ($1E)In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction SetReference for details).112467M–AVR–11/04Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack.
Note that the Stack is implemented as growingfrom higher memory locations to lower memory locations. This implies that a StackPUSH command decreases the Stack Pointer.The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located.
This Stack space in the data SRAM must be defined by theprogram before any subroutine calls are executed or interrupts are enabled. The StackPointer must be set to point above $60. The Stack Pointer is decremented by one whendata is pushed onto the Stack with the PUSH instruction, and it is decremented by twowhen the return address is pushed onto the Stack with subroutine call or interrupt.
TheStack Pointer is incremented by one when data is popped from the Stack with the POPinstruction, and it is incremented by two when data is popped from the Stack with returnfrom subroutine RET or return from interrupt RETI.The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in someimplementations of the AVR architecture is so small that only SPL is needed. In thiscase, the SPH Register will not be present.Bit15141312111098SP15SP14SP13SP12SP11SP10SP9SP8SPHSP7SP6SP5SP4SP3SP2SP1SP0SPL76543210Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W000000000000000076543210––––––––RAMPZ0Read/WriteRRRRRRRR/WInitial Value00000000Initial ValueRAM Page Z Select Register –RAMPZBitRAMPZ• Bits 7..1 – Res: Reserved BitsThese are reserved bits and will always read as zero.
When writing to this address location, write these bits to zero for compatibility with future devices.• Bit 0 – RAMPZ0: Extended RAM Page Z-pointerThe RAMPZ Register is normally used to select which 64K RAM Page is accessed bythe Z-pointer. As the ATmega128 does not support more than 64K of SRAM memory,this register is used only to select which page in the program memory is accessed whenthe ELPM/SPM instruction is used.
The different settings of the RAMPZ0 bit have thefollowing effects:RAMPZ0 = 0:Program memory address $0000 - $7FFF (lower 64K bytes) isaccessed by ELPM/SPMRAMPZ0 = 1:Program memory address $8000 - $FFFF (higher 64K bytes) isaccessed by ELPM/SPMNote that LPM is not affected by the RAMPZ setting.12ATmega1282467M–AVR–11/04ATmega128Instruction ExecutionTimingThis section describes the general access timing concepts for instruction execution.
TheAVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clocksource for the chip. No internal clock division is used.Figure 6 shows the parallel instruction fetches and instruction executions enabled by theHarvard architecture and the fast-access Register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results forfunctions per cost, functions per clocks, and functions per power-unit.Figure 6. The Parallel Instruction Fetches and Instruction ExecutionsT1T2T3T4clkCPU1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction FetchFigure 7 shows the internal timing concept for the Register file.
In a single clock cycle anALU operation using two register operands is executed, and the result is stored back tothe destination register.Figure 7. Single Cycle ALU OperationT1T2T3T4clkCPUTotal Execution TimeRegister Operands FetchALU Operation ExecuteResult Write BackReset and InterruptHandlingThe AVR provides several different interrupt sources. These interrupts and the separatereset vector each have a separate program vector in the program memory space. Allinterrupts are assigned individual enable bits which must be written logic one togetherwith the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.Depending on the Program Counter value, interrupts may be automatically disabledwhen Boot Lock bits BLB02 or BLB12 are programmed. This feature improves softwaresecurity.
See the section “Memory Programming” on page 288 for details.The lowest addresses in the program memory space are by default defined as the Resetand Interrupt vectors. The complete list of vectors is shown in “Interrupts” on page 57.The list also determines the priority levels of the different interrupts. The lower theaddress the higher is the priority level. RESET has the highest priority, and next is INT0– the External Interrupt Request 0.
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