ATmega128 (961723), страница 2
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The Port A output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port A pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port A pins are tri-stated when a resetcondition becomes active, even if the clock is not running.Port A also serves the functions of various special features of the ATmega128 as listedon page 70.Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit).
The Port B output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port B pins that are externally pulled low will source52467M–AVR–11/04current if the pull-up resistors are activated. The Port B pins are tri-stated when a resetcondition becomes active, even if the clock is not running.Port B also serves the functions of various special features of the ATmega128 as listedon page 71.Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port C output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port C pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated.
The Port C pins are tri-stated when a resetcondition becomes active, even if the clock is not running.Port C also serves the functions of special features of the ATmega128 as listed on page74. In ATmega103 compatibility mode, Port C is output only, and the port C pins are nottri-stated when a reset condition becomes active.Note:Port D (PD7..PD0)The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if theparts are not programmed before they are put on the PCB, PORTC will be output duringfirst power up, and until the ATmega103 compatibility mode is disabled.Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port D output buffers have symmetrical drive characteristics with both high sinkand source capability.
As inputs, Port D pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port D pins are tri-stated when a resetcondition becomes active, even if the clock is not running.Port D also serves the functions of various special features of the ATmega128 as listedon page 75.Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port E output buffers have symmetrical drive characteristics with both high sinkand source capability.
As inputs, Port E pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port E pins are tri-stated when a resetcondition becomes active, even if the clock is not running.Port E also serves the functions of various special features of the ATmega128 as listedon page 78.Port F (PF7..PF0)Port F serves as the analog inputs to the A/D Converter.Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.Port pins can provide internal pull-up resistors (selected for each bit). The Port F outputbuffers have symmetrical drive characteristics with both high sink and source capability.As inputs, Port F pins that are externally pulled low will source current if the pull-upresistors are activated. The Port F pins are tri-stated when a reset condition becomesactive, even if the clock is not running.
If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Resetoccurs.The TDO pin is tri-stated unless TAP states that shift out data are entered.Port F also serves the functions of the JTAG interface.In ATmega103 compatibility mode, Port F is an input Port only.Port G (PG4..PG0)6Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port G output buffers have symmetrical drive characteristics with both high sinkand source capability.
As inputs, Port G pins that are externally pulled low will sourceATmega1282467M–AVR–11/04ATmega128current if the pull-up resistors are activated. The Port G pins are tri-stated when a resetcondition becomes active, even if the clock is not running.Port G also serves the functions of various special features.The port G pins are tri-stated when a reset condition becomes active, even if the clock isnot running.In ATmega103 compatibility mode, these pins only serves as strobes signals to theexternal memory as well as input to the 32 kHz Oscillator, and the pins are initialized toPG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active,even if the clock is not running. PG3 and PG4 are oscillator pins.RESETReset input.
A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table19 on page 48. Shorter pulses are not guaranteed to generate a reset.XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting Oscillator amplifier.AVCCAVCC is the supply voltage pin for Port F and the A/D Converter. It should be externallyconnected to VCC, even if the ADC is not used.
If the ADC is used, it should be connected to VCC through a low-pass filter.AREFAREF is the analog reference pin for the A/D Converter.PENPEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enterthe SPI Serial Programming mode. PEN has no function during normal operation.About CodeExamplesThis datasheet contains simple code examples that briefly show how to use variousparts of the device.
These code examples assume that the part specific header file isincluded before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Pleaseconfirm with the C compiler documentation for more details.72467M–AVR–11/04AVR CPU CoreIntroductionThis section discusses the AVR core architecture in general. The main function of theCPU core is to ensure correct program execution. The CPU must therefore be able toaccess memories, perform calculations, control peripherals and handle interrupts.Architectural OverviewFigure 3. Block Diagram of the AVR ArchitectureData Bus 8-bitFlashProgramMemoryProgramCounterStatusand Control32 x 8GeneralPurposeRegistrersControl LinesDirect AddressingInstructionDecoderIndirect AddressingInstructionRegisterInterruptUnitSPIUnitWatchdogTimerALUAnalogComparatorI/O Module1DataSRAMI/O Module 2I/O Module nEEPROMI/O LinesIn order to maximize performance and parallelism, the AVR uses a Harvard architecture– with separate memories and buses for program and data.
Instructions in the programmemory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This conceptenables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.The fast-access Register file contains 32 x 8-bit general purpose working registers witha single clock cycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU)operation. In a typical ALU operation, two operands are output from the Register file, theoperation is executed, and the result is stored back in the Register file – in one clockcycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers forData Space addressing – enabling efficient address calculations. One of the theseaddress pointers can also be used as an address pointer for look up tables in Flash Program memory.
These added function registers are the 16-bit X-register, Y-register andZ-register, described later in this section.The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After8ATmega1282467M–AVR–11/04ATmega128an arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.Program flow is provided by conditional and unconditional jump and call instructions,able to directly address the whole address space. Most AVR instructions have a single16-bit word format.
Every program memory address contains a 16- or 32-bit instruction.Program Flash memory space is divided in two sections, the Boot Program section andthe Application Program section. Both sections have dedicated Lock bits for write andread/write protection. The SPM instruction that writes into the Application Flash Memorysection must reside in the Boot Program section.During interrupts and subroutine calls, the return address Program Counter (PC) isstored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the stack size is only limited by the total SRAM size and the usage of theSRAM. All user programs must initialize the SP in the reset routine (before subroutinesor interrupts are executed). The Stack Pointer – SP – is read/write accessible in the I/Ospace.
The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.The memory spaces in the AVR architecture are all linear and regular memory maps.A flexible interrupt module has its control registers in the I/O space with an additionalglobal interrupt enable bit in the Status Register.
All interrupts have a separate interruptvector in the interrupt vector table. The interrupts have priority in accordance with theirinterrupt vector position. The lower the interrupt vector address, the higher the priority.The I/O memory space contains 64 addresses which can be accessed directly, or as theData Space locations following those of the Register file, $20 - $5F.
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