ATmega128 (961723), страница 4
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The interrupt vectors can be moved to the start of theboot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).Refer to “Interrupts” on page 57 for more information. The Reset vector can also bemoved to the start of the boot Flash section by programming the BOOTRST fuse, see“Boot Loader Support – Read-While-Write Self-Programming” on page 275.132467M–AVR–11/04When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interruptsare disabled. The user software can write logic one to the I-bit to enable nested interrupts.
All enabled interrupts can then interrupt the current interrupt routine. The I-bit isautomatically set when a Return from Interrupt instruction – RETI – is executed.There are basically two types of interrupts. The first type is triggered by an event thatsets the interrupt flag. For these interrupts, the Program Counter is vectored to theactual interrupt vector in order to execute the interrupt handling routine, and hardwareclears the corresponding interrupt flag. Interrupt flags can also be cleared by writing alogic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one ormore interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bitis set, and will then be executed by order of priority.The second type of interrupts will trigger as long as the interrupt condition is present.These interrupts do not necessarily have interrupt flags.
If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine.
This must be handled bysoftware.When using the CLI instruction to disable interrupts, the interrupts will be immediatelydisabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used toavoid interrupts during the timed EEPROM write sequence.Assembly Code Examplein r16, SREGcli; store SREG value; disable interrupts during timed sequencesbi EECR, EEMWE; start EEPROM writesbi EECR, EEWEout SREG, r16; restore SREG value (I-bit)C Code Examplechar cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */__disable_interrupt();EECR |= (1<<EEMWE); /* start EEPROM write */EECR |= (1<<EEWE);SREG = cSREG; /* restore SREG value (I-bit) */14ATmega1282467M–AVR–11/04ATmega128When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending interrupts, as shown in this example.Assembly Code Examplesei; set global interrupt enablesleep; enter sleep, waiting for interrupt; note: will enter sleep before any pending; interrupt(s)C Code Example__enable_interrupt(); /* set global interrupt enable */__sleep(); /* enter sleep, waiting for interrupt *//* note: will enter sleep before any pending interrupt(s) */Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is four clock cyclesminimum.
After four clock cycles, the program vector address for the actual interrupthandling routine is executed. During this 4-clock cycle period, the Program Counter ispushed onto the Stack. The vector is normally a jump to the interrupt routine, and thisjump takes three clock cycles. If an interrupt occurs during execution of a multi-cycleinstruction, this instruction is completed before the interrupt is served. If an interruptoccurs when the MCU is in Sleep mode, the interrupt execution response time isincreased by four clock cycles. This increase comes in addition to the start-up time fromthe selected sleep mode.A return from an interrupt handling routine takes four clock cycles. During these 4-clockcycles, the Program Counter (two bytes) is popped back from the Stack, the StackPointer is incremented by two, and the I-bit in SREG is set.152467M–AVR–11/04AVR ATmega128MemoriesThis section describes the different memories in the ATmega128.
The AVR architecturehas two main memory spaces, the Data Memory and the Program Memory space. Inaddition, the ATmega128 features an EEPROM Memory for data storage. All threememory spaces are linear and regular.In-SystemReprogrammable FlashProgram MemoryThe ATmega128 contains 128K bytes On-chip In-System Reprogrammable Flash memory for program storage.
Since all AVR instructions are 16 or 32 bits wide, the Flash isorganized as 64K x 16. For software security, the Flash Program memory space isdivided into two sections, Boot Program section and Application Program section.The Flash memory has an endurance of at least 10,000 write/erase cycles. TheATmega128 Program Counter (PC) is 16 bits wide, thus addressing the 64K programmemory locations. The operation of Boot Program section and associated Boot Lockbits for software protection are described in detail in “Boot Loader Support – ReadWhile-Write Self-Programming” on page 275. “Memory Programming” on page 288 contains a detailed description on Flash programming in SPI, JTAG, or ParallelProgramming mode.Constant tables can be allocated within the entire program memory address space (seethe LPM – Load Program Memory and ELPM – Extended Load Program Memoryinstruction description).Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 13.Figure 8.
Program Memory MapProgram Memory$0000Application Flash SectionBoot Flash Section$FFFF16ATmega1282467M–AVR–11/04ATmega128SRAM Data MemoryThe ATmega128 supports two different configurations for the SRAM data memory aslisted in Table 1.Table 1. Memory ConfigurationsConfigurationInternal SRAM Data MemoryExternal SRAM Data MemoryNormal mode4096up to 64KATmega103 Compatibilitymode4000up to 64KFigure 9 shows how the ATmega128 SRAM Memory is organized.The ATmega128 is a complex microcontroller with more peripheral units than can besupported within the 64 location reserved in the Opcode for the IN and OUT instructions.For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD andLD/LDS/LDD instructions can be used.
The Extended I/O space does not exist when theATmega128 is in the ATmega103 compatibility mode.In normal mode, the first 4352 Data Memory locations address both the Register file, theI/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locationsaddress the Register file, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096 locations address the internal dataSRAM.In ATmega103 compatibility mode, the first 4096 Data Memory locations address boththe Register file, the I/O Memory and the internal data SRAM. The first 32 locationsaddress the Register file, the next 64 location the standard I/O memory, and the next4000 locations address the internal data SRAM.An optional external data SRAM can be used with the ATmega128. This SRAM willoccupy an area in the remaining address locations in the 64K address space.
This areastarts at the address following the internal SRAM. The Register file, I/O, Extended I/Oand Internal SRAM occupies the lowest 4352 bytes in normal mode, and the lowest4096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so whenusing 64KB (65536 bytes) of External Memory, 61184 Bytes of External Memory areavailable in normal mode, and 61440 Bytes in ATmega103 compatibility mode.
See“External Memory Interface” on page 24 for details on how to take advantage of theexternal memory map.When the addresses accessing the SRAM memory space exceeds the internal datamemory locations, the external data SRAM is accessed using the same instructions asfor the internal data memory access. When the internal data memories are accessed,the read and write strobe pins (PG0 and PG1) are inactive during the whole accesscycle. External SRAM operation is enabled by setting the SRE bit in the MCUCRRegister.Accessing external SRAM takes one additional clock cycle per byte compared to accessof the internal SRAM.
This means that the commands LD, ST, LDS, STS, LDD, STD,PUSH, and POP take one additional clock cycle. If the Stack is placed in externalSRAM, interrupts, subroutine calls and returns take three clock cycles extra because thetwo-byte program counter is pushed and popped, and external memory access does nottake advantage of the internal pipe-line memory access. When external SRAM interfaceis used with wait-state, one-byte external access takes two, three, or four additionalclock cycles for one, two, and three wait-states respectively.
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