ATmega128 (961723), страница 6
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Secondly, the CPU itself can execute instructions incorrectly, if thesupply voltage is too low.EEPROM data corruption can easily be avoided by following this designrecommendation:232467M–AVR–11/04Keep the AVR RESET active (low) during periods of insufficient power supply voltage.This can be done by enabling the internal Brown-out Detector (BOD). If the detectionlevel of the internal BOD does not match the needed detection level, an external lowVCC Reset Protection circuit can be used. If a reset occurs while a write operation is inprogress, the write operation will be completed provided that the power supply voltage issufficient.I/O MemoryThe I/O space definition of the ATmega128 is shown in “Register Summary” on page364.All ATmega128 I/Os and peripherals are placed in the I/O space.
All I/O locations maybe accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring databetween the 32 general purpose working registers and the I/O space. I/O registerswithin the address range $00 - $1F are directly bit-accessible using the SBI and CBIinstructions. In these registers, the value of single bits can be checked by using theSBIS and SBIC instructions. Refer to the instruction set section for more details. Whenusing the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must beused. When addressing I/O registers as data space using LD and ST instructions, $20must be added to these addresses.
The ATmega128 is a complex microcontroller withmore peripheral units than can be supported within the 64 location reserved in Opcodefor the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM,only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/Ospace is replaced with SRAM locations when the ATmega128 is in the ATmega103compatibility mode.For compatibility with future devices, reserved bits should be written to zero if accessed.Reserved I/O memory addresses should never be written.Some of the status flags are cleared by writing a logical one to them.
Note that the CBIand SBI instructions will operate on all bits in the I/O register, writing a one back into anyflag read as set, thus clearing the flag. The CBI and SBI instructions work with registers$00 to $1F only.The I/O and peripherals control registers are explained in later sections.External MemoryInterfaceWith all the features the External Memory Interface provides, it is well suited to operateas an interface to memory devices such as External SRAM and Flash, and peripheralssuch as LCD-display, A/D, and D/A.
The main features are:• Four different wait-state settings (including no wait-state).• Independent wait-state setting for different extErnal Memory sectors (configurable sectorsize).• The number of bits dedicated to address high byte is selectable.• Bus-keepers on data lines to minimize current consumption (optional).Overview24When the eXternal MEMory (XMEM) is enabled, address space outside the internalSRAM becomes available using the dedicated External Memory pins (see Figure 1 onpage 2, Table 27 on page 70, Table 33 on page 74, and Table 45 on page 82). Thememory configuration is shown in Figure 11.ATmega1282467M–AVR–11/04ATmega128Figure 11.
External Memory with Sector SelectMemory Configuration BMemory Configuration A0x00000x0000Internal memoryInternal memory0x0FFF0x10000x10FF0x1100Lower sectorSRW01SRW00SRW10SRL[2..0]External Memory(0-60K x 8)External Memory(0-60K x 8)Upper sectorSRW11SRW100xFFFFNote:ATmega103 CompatibilityATmega128 in non ATmega103 compatibility mode: Memory Configuration A is available(Memory Configuration B N/A)ATmega128 in ATmega103 compatibility mode: Memory Configuration B is available(Memory Configuration A N/A)Both External Memory Control Registers (XMCRA and XMCRB) are placed in ExtendedI/O space.
In ATmega103 compatibility mode, these registers are not available, and thefeatures selected by these registers are not available. The device is still ATmega103compatible, as these features did not exist in ATmega103. The limitations inATmega103 compatibility mode are:•Using the External MemoryInterface0xFFFFOnly two wait-states settings are available (SRW1n = 0b00 and SRW1n = 0b01).•The number of bits that are assigned to address high byte are fixed.•The External Memory section can not be divided into sectors with different waitstate settings.•Bus-keeper is not available.•RD, WR and ALE pins are output only (Port G in ATmega128).The interface consists of:•AD7:0: Multiplexed low-order address bus and data bus.•A15:8: High-order address bus (configurable number of bits).•ALE: Address latch enable.•RD: Read strobe.•WR: Write strobe.252467M–AVR–11/04The control bits for the External Memory Interface are located in three registers, theMCU Control Register – MCUCR, the External Memory Control Register A – XMCRA,and the External Memory Control Register B – XMCRB.When the XMEM interface is enabled, the XMEM interface will override the setting in thedata direction registers that corresponds to the ports dedicated to the XMEM interface.For details about the port override, see the alternate functions in section “I/O Ports” onpage 63.
The XMEM interface will auto-detect whether an access is internal or external.If the access is external, the XMEM interface will output address, data, and the controlsignals on the ports according to Figure 13 (this figure shows the wave forms withoutwait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE islow during a data transfer. When the XMEM interface is enabled, also an internal accesswill cause activity on address, data and ALE ports, but the RD and WR strobes will nottoggle during internal access.
When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface isdisabled, the address space above the internal SRAM boundary is not mapped into theinternal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR usingan octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.Address Latch RequirementsDue to the high-speed operation of the XRAM interface, the address latch must beselected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.When operating at conditions above these frequencies, the typical old style 74HC serieslatch becomes inadequate. The External Memory Interface is designed in compliance tothe 74AHC series latch.
However, most latches can be used as long they comply withthe main timing parameters. The main parameters for the address latch are:•D to Q propagation delay (tPD).•Data setup time before G low (tSU).•Data (address) hold time after G low (TH).The External Memory Interface is designed to guaranty minimum address hold timeafter G is asserted low of th = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in “External Data MemoryTiming” Tables 137 through Tables 144 on pages 330 - 332. The D-to-Q propagationdelay (tPD) must be taken into consideration when calculating the access time requirement of the external component. The data setup time before G low (t SU ) must notexceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent on thecapacitive load).Figure 12. External SRAM Connected to the AVRD[7:0]AD7:0DALEGAVRA15:8RDWR26QA[7:0]SRAMA[15:8]RDWRATmega1282467M–AVR–11/04ATmega128Pull-up and Bus-keeperThe pull-ups on the AD7:0 ports may be activated if the corresponding Port register iswritten to one.
To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keepercan be disabled and enabled in software as described in “External Memory Control Register B – XMCRB” on page 31. When enabled, the bus-keeper will ensure a defined logiclevel (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated bythe XMEM interface.TimingExternal Memory devices have different timing requirements. To meet these requirements, the ATmega128 XMEM interface provides four different wait-states as shown inTable 4. It is important to consider the timing specification of the External Memorydevice before selecting the wait-state.
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