ATmega128 (961723), страница 11
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If the inputbuffer is enabled and the input signal is left floating or have an analog signal level closeto VCC/2, the input buffer will use excessive power.452467M–AVR–11/04JTAG Interface and On-chipDebug SystemIf the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Powerdown or Power save sleep mode, the main clock source remains enabled. In thesesleep modes, this will contribute significantly to the total current consumption. There arethree alternative ways to avoid this:•Disable OCDEN Fuse.•Disable JTAGEN Fuse.•Write one to the JTD bit in MCUCSR.The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAPcontroller is not shifting data. If the hardware connected to the TDO pin does not pull upthe logic level, power consumption will increase.
Note that the TDI pin for the nextdevice in the scan chain contains a pull-up that avoids this problem. Writing the JTD bitin the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables theJTAG interface.46ATmega1282467M–AVR–11/04ATmega128System Control andResetResetting the AVRDuring Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP– absolute jump – instruction to the reset handling routine.
If the program never enablesan interrupt source, the interrupt vectors are not used, and regular program code can beplaced at these locations. This is also the case if the Reset Vector is in the Applicationsection while the interrupt vectors are in the Boot section or vice versa. The circuit diagram in Figure 22 shows the reset logic. Table 19 defines the electrical parameters ofthe reset circuitry.The I/O ports of the AVR are immediately reset to their initial state when a reset sourcegoes active.
This does not require any clock source to be running.After all reset sources have gone inactive, a delay counter is invoked, stretching theinternal reset. This allows the power to reach a stable level before normal operationstarts. The time-out period of the delay counter is defined by the user through theCKSEL fuses. The different selections for the delay period are presented in “ClockSources” on page 35.Reset SourcesThe ATmega128 has five sources of reset:•Power-on Reset.
The MCU is reset when the supply voltage is below the Power-onReset threshold (VPOT).•External Reset. The MCU is reset when a low level is present on the RESET pin forlonger than the minimum pulse length.•Watchdog Reset. The MCU is reset when the Watchdog Timer period expires andthe Watchdog is enabled.•Brown-out Reset. The MCU is reset when the supply voltage VCC is below theBrown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.•JTAG AVR Reset.
The MCU is reset as long as there is a logic one in the ResetRegister, one of the scan chains of the JTAG system. Refer to the section “IEEE1149.1 (JTAG) Boundary-scan” on page 254 for details.472467M–AVR–11/04Figure 22. Reset LogicDATA BUSDQLQMCU Control and StatusRegister (MCUCSR)PORFBORFEXTRFWDRFJTRFPENPull-up ResistorPower-On ResetCircuitBrown-OutReset CircuitBODENBODLEVELPull-up ResistorSPIKEFILTERReset CircuitJTAG ResetRegisterCOUNTER RESETRESETWatchdogTimerWatchdogOscillatorClockGeneratorCKDelay CountersTIMEOUTCKSEL[3:0]SUT[1:0]Table 19. Reset CharacteristicsSymbolVPOTConditionMinTypMaxUnitsPower-on ResetThreshold Voltage(rising)1.42.3VPower-on ResetThreshold Voltage(falling)(1)1.32.3V0.85 VCCVVRSTRESET Pin ThresholdVoltage0.2 VCCtRSTPulse width on RESETPin1.5Brown-out ResetThreshold Voltage(2)BODLEVEL = 12.42.62.9VBOTBODLEVEL = 03.74.04.5Minimum low voltageperiod for Brown-outDetectionBODLEVEL = 12µstBODBODLEVEL = 02µsVHYSTBrown-out Detectorhysteresis100mVNotes:48ParameterµsV1.
The Power-on Reset will not work unless the supply voltage has been below VPOT(falling)ATmega1282467M–AVR–11/04ATmega1282. VBOT may be below nominal minimum operating voltage for some devices. Fordevices where this is the case, the device is tested down to VCC = VBOT during theproduction test. This guarantees that a Brown-out Reset will occur before VCC dropsto a voltage where correct operation of the microcontroller is no longer guaranteed.The test is performed using BODLEVEL=1 for ATmega128L and BODLEVEL=0 forATmega128. BODLEVEL=1 is not applicable for ATmega128.Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
The detection level is defined in Table 19. The POR is activated whenever VCC is below thedetection level. The POR circuit can be used to trigger the Start-up Reset, as well as todetect a failure in supply voltage.A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determineshow long the device is kept in RESET after VCC rise. The RESET signal is activatedagain, without any delay, when VCC decreases below the detection level.Figure 23. MCU Start-up, RESET Tied to VCC.VCCRESETVPOTVRSTtTOUTTIME-OUTINTERNALRESETFigure 24. MCU Start-up, RESET Extended ExternallyVCCRESETTIME-OUTVPOTVRSTtTOUTINTERNALRESETExternal ResetAn External Reset is generated by a low level on the RESET pin. Reset pulses longerthan the minimum pulse width (see Table 19) will generate a reset, even if the clock isnot running.
Shorter pulses are not guaranteed to generate a reset. When the appliedsignal reaches the Reset Threshold Voltage – VRST on its positive edge, the delaycounter starts the MCU after the Time-out period tTOUT has expired.492467M–AVR–11/04Figure 25. External Reset During OperationCCBrown-out DetectionATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during operation by comparing it to a fixed trigger level.
The trigger level for theBOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spikefree Brown-out Detection. The hysteresis on the detection level should be interpreted asVBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD isenabled (BODEN programmed), and VCC decreases to a value below the trigger level(VBOT- in Figure 26), the Brown-out Reset is immediately activated. When VCC increasesabove the trigger level (VBOT+ in Figure 26), the delay counter starts the MCU after thetime-out period tTOUT has expired.The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger levelfor longer than tBOD given in Table 19.Figure 26.
Brown-out Reset During OperationVCCVBOT-VBOT+RESETTIME-OUTtTOUTINTERNALRESET50ATmega1282467M–AVR–11/04ATmega128Watchdog ResetWhen the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out periodtTOUT. Refer to page 52 for details on operation of the Watchdog Timer.Figure 27. Watchdog Reset During OperationCCCKMCU Control and StatusRegister – MCUCSRThe MCU Control and Status Register provides information on which reset sourcecaused an MCU reset.Bit76543210JTD––JTRFWDRFBORFEXTRFPORFRead/WriteR/WRRR/WR/WR/WR/WR/WInitial Value000MCUCSRSee Bit DescriptionNote that only EXTRF and PORF are available in ATmega103 compatibility mode.• Bit 4 – JTRF: JTAG Reset FlagThis bit is set if a reset is being caused by a logic one in the JTAG Reset Registerselected by the JTAG instruction AVR_RESET.
This bit is reset by a Power-on Reset, orby writing a logic zero to the flag.• Bit 3 – WDRF: Watchdog Reset FlagThis bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.• Bit 2 – BORF: Brown-out Reset FlagThis bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.• Bit 1 – EXTRF: External Reset FlagThis bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or bywriting a logic zero to the flag.• Bit 0 – PORF: Power-On Reset FlagThis bit is set if a Power-on Reset occurs.
The bit is reset only by writing a logic zero tothe flag.To make use of the reset flags to identify a reset condition, the user should read andthen reset the MCUCSR as early as possible in the program. If the register is clearedbefore another reset occurs, the source of the reset can be found by examining the resetflags.512467M–AVR–11/04Internal VoltageReferenceATmega128 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC. The2.56V reference to the ADC is generated from the internal bandgap reference.Voltage Reference EnableSignals and Start-up TimeThe voltage reference has a start-up time that may influence the way it should be used.The start-up time is given in Table 20.
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