ATmega128 (961723), страница 15
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WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clkI/O,SLEEP, and PUD are common to all ports. All other signals are unique for each pin.ATmega1282467M–AVR–11/04ATmega128Table 26 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 33 are not shown in the succeeding tables.
The overriding signals are generated internally in the modules having the alternate function.Table 26. Generic Description of Overriding Signals for Alternate Functions.SignalNameFull NameDescriptionPUOEPull-upOverride EnableIf this signal is set, the pull-up enable is controlled by thePUOV signal. If this signal is cleared, the pull-up isenabled when {DDxn, PORTxn, PUD} = 0b010.PUOVPull-upOverride ValueIf PUOE is set, the pull-up is enabled/disabled whenPUOV is set/cleared, regardless of the setting of theDDxn, PORTxn, and PUD Register bits.DDOEData DirectionOverride EnableIf this signal is set, the Output Driver Enable is controlledby the DDOV signal. If this signal is cleared, the Outputdriver is enabled by the DDxn Register bit.DDOVData DirectionOverride ValueIf DDOE is set, the Output Driver is enabled/disabledwhen DDOV is set/cleared, regardless of the setting of theDDxn Register bit.PVOEPort ValueOverride EnableIf this signal is set and the Output Driver is enabled, theport value is controlled by the PVOV signal.
If PVOE iscleared, and the Output Driver is enabled, the port Valueis controlled by the PORTxn Register bit.PVOVPort ValueOverride ValueIf PVOE is set, the port value is set to PVOV, regardless ofthe setting of the PORTxn Register bit.DIEOEDigital InputEnable OverrideEnableIf this bit is set, the Digital Input Enable is controlled by theDIEOV signal. If this signal is cleared, the Digital InputEnable is determined by MCU-state (Normal mode, Sleepmodes).DIEOVDigital InputEnable OverrideValueIf DIEOE is set, the Digital Input is enabled/disabled whenDIEOV is set/cleared, regardless of the MCU state(Normal mode, Sleep modes).DIDigital InputThis is the Digital Input to alternate functions.
In thefigure, the signal is connected to the output of the schmitttrigger but before the synchronizer. Unless the DigitalInput is used as a clock source, the module with thealternate function will use its own synchronizer.AIOAnalogInput/outputThis is the Analog Input/output to/from alternate functions.The signal is connected directly to the pad, and can beused bi-directionally.The following subsections shortly describes the alternate functions for each port, andrelates the overriding signals to the alternate function. Refer to the alternate functiondescription for further details.692467M–AVR–11/04Special Function IO Register –SFIORBit76543210TSM–––ACMEPUDPSR0PSR321Read/WriteR/WRRRR/WR/WR/WR/WInitial Value00000000SFIOR• Bit 2 – PUD: Pull-up disableWhen this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxnand PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).See “Configuring the Pin” on page 64 for more details about this feature.Alternate Functions of Port AThe Port A has an alternate function as the address low byte and data lines for theExternal Memory Interface.Table 27.
Port A Pins Alternate FunctionsPort PinAlternate FunctionPA7AD7 (External memory interface address and data bit 7)PA6AD6 (External memory interface address and data bit 6)PA5AD5 (External memory interface address and data bit 5)PA4AD4 (External memory interface address and data bit 4)PA3AD3 (External memory interface address and data bit 3)PA2AD2 (External memory interface address and data bit 2)PA1AD1 (External memory interface address and data bit 1)PA0AD0 (External memory interface address and data bit 0)Table 28 and Table 29 relates the alternate functions of Port A to the overriding signalsshown in Figure 33 on page 68.Table 28. Overriding Signals for Alternate Functions in PA7..PA4SignalNamePA7/AD7PUOESREPA5/AD5PA4/AD4SRESRESREPUOV~(WR | ADA ) •PORTA7 • PUD~(WR | ADA) •PORTA6 • PUD~(WR | ADA) •PORTA5 • PUD~(WR | ADA) •PORTA4 • PUDDDOESRESRESRESREDDOVWR | ADAWR | ADAWR | ADAWR | ADAPVOESRESRESRESREPVOVA7 • ADA | D7OUTPUT • WRA6 • ADA | D6OUTPUT • WRA5 • ADA | D5OUTPUT • WRA4 • ADA | D4OUTPUT • WRDIEOE0000DIEOV0000DID7 INPUTD6 INPUTD5 INPUTD4 INPUTAIO––––Note:70(1)PA6/AD61.
ADA is short for ADdress Active and represents the time when address is output. See“External Memory Interface” on page 24 for details.ATmega1282467M–AVR–11/04ATmega128Table 29. Overriding Signals for Alternate Functions in PA3..PA0Alternate Functions of Port BSignalNamePA3/AD3PA2/AD2PA1/AD1PA0/AD0PUOESRESRESRESREPUOV~(WR | ADA) •PORTA3 • PUD~(WR | ADA) •PORTA2 • PUD~(WR | ADA) •PORTA1 • PUD~(WR | ADA) •PORTA0 • PUDDDOESRESRESRESREDDOVWR | ADAWR | ADAWR | ADAWR | ADAPVOESRESRESRESREPVOVA3 • ADA | D3OUTPUT • WRA2• ADA | D2OUTPUT • WRA1 • ADA | D1OUTPUT • WRA0 • ADA | D0OUTPUT • WRDIEOE0000DIEOV0000DID3 INPUTD2 INPUTD1 INPUTD0 INPUTAIO––––The Port B pins with alternate functions are shown in Table 30.Table 30.
Port B Pins Alternate FunctionsPort PinAlternate FunctionsPB7OC2/OC1C(1) (Output Compare and PWM Output for Timer/Counter2 or OutputCompare and PWM Output C for Timer/Counter1)PB6OC1B (Output Compare and PWM Output B for Timer/Counter1)PB5OC1A (Output Compare and PWM Output A for Timer/Counter1)PB4OC0 (Output Compare and PWM Output for Timer/Counter0)PB3MISO (SPI Bus Master Input/Slave Output)PB2MOSI (SPI Bus Master Output/Slave Input)PB1SCK (SPI Bus Serial Clock)PB0SS (SPI Slave Select input)Note:1. OC1C not applicable in ATmega103 compatibility mode.The alternate pin configuration is as follows:• OC2/OC1C, Bit 7OC2, Output Compare Match output: The PB7 pin can serve as an external output forthe Timer/Counter2 Output Compare.
The pin has to be configured as an output (DDB7set “one”) to serve this function. The OC2 pin is also the output pin for the PWM modetimer function.OC1C, Output Compare Match C output: The PB7 pin can serve as an external outputfor the Timer/Counter1 Output Compare C. The pin has to be configured as an output(DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for thePWM mode timer function.• OC1B, Bit 6712467M–AVR–11/04OC1B, Output Compare Match B output: The PB6 pin can serve as an external outputfor the Timer/Counter1 Output Compare B.
The pin has to be configured as an output(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWMmode timer function.• OC1A, Bit 5OC1A, Output Compare Match A output: The PB5 pin can serve as an external outputfor the Timer/Counter1 Output Compare A. The pin has to be configured as an output(DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWMmode timer function.• OC0, Bit 4OC0, Output Compare Match output: The PB4 pin can serve as an external output forthe Timer/Counter0 Output Compare.
The pin has to be configured as an output (DDB4set (one)) to serve this function. The OC0 pin is also the output pin for the PWM modetimer function.• MISO – Port B, Bit 3MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI isenabled as a master, this pin is configured as an input regardless of the setting ofDDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled byDDB3. When the pin is forced to be an input, the pull-up can still be controlled by thePORTB3 bit.• MOSI – Port B, Bit 2MOSI: SPI Master Data output, Slave Data input for SPI channel.
When the SPI isenabled as a slave, this pin is configured as an input regardless of the setting of DDB2.When the SPI is enabled as a master, the data direction of this pin is controlled byDDB2. When the pin is forced to be an input, the pull-up can still be controlled by thePORTB2 bit.• SCK – Port B, Bit 1SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI isenabled as a slave, this pin is configured as an input regardless of the setting of DDB1.When the SPI is enabled as a master, the data direction of this pin is controlled byDDB1.
When the pin is forced to be an input, the pull-up can still be controlled by thePORTB1 bit.• SS – Port B, Bit 0SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configuredas an input regardless of the setting of DDB0. As a slave, the SPI is activated when thispin is driven low. When the SPI is enabled as a master, the data direction of this pin iscontrolled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.Table 31 and Table 32 relate the alternate functions of Port B to the overriding signalsshown in Figure 33 on page 68.
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