ATmega128 (961723), страница 18
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Whenthe external interrupt is enabled and is configured as level triggered, the interrupt willtrigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems andtheir Distribution” on page 34. Low level interrupts and the edge interrupt on INT3:0 aredetected asynchronously. This implies that these interrupts can be used for waking thepart also from sleep modes other than Idle mode.
The I/O clock is halted in all sleepmodes except Idle mode.Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. This makes the MCUless sensitive to noise. The changed level is sampled twice by the Watchdog Oscillatorclock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C.
Thefrequency of the Watchdog Oscillator is voltage dependent as shown in the “ElectricalCharacteristics” on page 321. The MCU will wake up if the input has the required levelduring this sampling or if it is held until the end of the start-up time. The start-up time isdefined by the SUT fuses as described in “Clock Systems and their Distribution” onpage 34. If the level is sampled twice by the Watchdog Oscillator clock but disappearsbefore the end of the start-up time, the MCU will still wake up, but no interrupt will begenerated. The required level must be held long enough for the MCU to complete thewake up to trigger the level interrupt.External Interrupt ControlRegister A – EICRABit76543210ISC31ISC30ISC21ISC20ISC11ISC10ISC01ISC00Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000EICRAThis Register can not be reached in ATmega103 compatibility mode, but the initial valuedefines INT3:0 as low level interrupts, as in ATmega103.• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense ControlBitsThe External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flagand the corresponding interrupt mask in the EIMSK is set.
The level and edges on theexternal pins that activate the interrupts are defined in Table 48. Edges on INT3..INT0are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulsewidth given in Table 49 will generate an interrupt. Shorter pulses are not guaranteed togenerate an interrupt. If low level interrupt is selected, the low level must be held untilthe completion of the currently executing instruction to generate an interrupt. If enabled,a level triggered interrupt will generate an interrupt request as long as the pin is heldlow. When changing the ISCn bit, an interrupt can occur.
Therefore, it is recommendedto first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, theISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing alogical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is reenabled.872467M–AVR–11/04Table 48.
Interrupt Sense Control(1)ISCn1ISCn000The low level of INTn generates an interrupt request.01Reserved10The falling edge of INTn generates asynchronously an interrupt request.1Note:Description1The rising edge of INTn generates asynchronously an interrupt request.1.
n = 3, 2, 1or 0.When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing itsInterrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur whenthe bits are changed.Table 49. Asynchronous External Interrupt CharacteristicsSymbolConditionMinTypMinimum pulse width forasynchronous external interrupttINTExternal Interrupt ControlRegister B – EICRBParameterBitMaxUnits50ns76543210ISC71ISC70ISC61ISC60ISC51ISC50ISC41ISC40Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000EICRB• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense ControlBitsThe External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flagand the corresponding interrupt mask in the EIMSK is set.
The level and edges on theexternal pins that activate the interrupts are defined in Table 50. The value on theINT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.
Shorter pulsesare not guaranteed to generate an interrupt. Observe that CPU clock frequency can belower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt isselected, the low level must be held until the completion of the currently executinginstruction to generate an interrupt. If enabled, a level triggered interrupt will generate aninterrupt request as long as the pin is held low.Table 50. Interrupt Sense Control(1)ISCn1ISCn000The low level of INTn generates an interrupt request.01Any logical change on INTn generates an interrupt request10The falling edge between two samples of INTn generates an interruptrequest.1Note:88DescriptionThe rising edge between two samples of INTn generates an interruptrequest.1. n = 7, 6, 5 or 4.When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing itsInterrupt Enable bit in the EIMSK Register.
Otherwise an interrupt can occur whenthe bits are changed.1ATmega1282467M–AVR–11/04ATmega128External Interrupt MaskRegister – EIMSKBit76543210INT7INT6INT5INT4INT3INT2INT1IINT0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000EIMSK• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 EnableWhen an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) isset (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defineswhether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as anoutput.
This provides a way of generating a software interrupt.External Interrupt FlagRegister – EIFRBit76543210INTF7INTF6INTF5INTF4INTF3INTF2INTF1IINTF0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000EIFR• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit,INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag iscleared when the interrupt routine is executed. Alternatively, the flag can be cleared bywriting a logical one to it.
These flags are always cleared when INT7:0 are configured aslevel interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”on page 67 for more information.892467M–AVR–11/048-bit Timer/Counter0with PWM andAsynchronousOperationTimer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. Themain features are:• Single Channel Counter• Clear Timer on Compare Match (Auto Reload)• Glitch-free, Phase Correct Pulse Width Modulator (PWM)• Frequency Generator• 10-bit Clock Prescaler• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O ClockOverviewA simplified block diagram of the 8-bit Timer/Counter is shown in Figure 34.
For theactual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessibleI/O registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/Oregister and bit locations are listed in the “8-bit Timer/Counter Register Description” onpage 101.Figure 34. 8-bit Timer/Counter Block DiagramTCCRncountTOVn(Int.Req.)clearControl LogicdirectionclkTnTOSC1BOTTOMTOPPrescalerT/COscillatorTOSC2Timer/CounterTCNTn=0= 0xFFOCn(Int.Req.)WaveformGeneration=clk I/OOCnDATABUSOCRnSynchronized Status flagsclk I/OSynchronization Unitclk ASYStatus flagsASSRnasynchronous modeselect (ASn)RegistersThe Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt FlagRegister (TIFR).
All interrupts are individually masked with the Timer Interrupt MaskRegister (TIMSK). TIFR and TIMSK are not shown in the figure since these registers areshared by other timer units.The Timer/Counter can be clocked internally, via the prescaler, or asynchronouslyclocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous90ATmega1282467M–AVR–11/04ATmega128operation is controlled by the Asynchronous Status Register (ASSR). The Clock Selectlogic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. Theoutput from the clock select logic is referred to as the timer clock (clkT0).The double buffered Output Compare Register (OCR0) is compared with theTimer/Counter value at all times.
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