ATmega128 (961723), страница 20
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In normal operation the Timer/Counter overflow flag(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0flag in this case behaves like a ninth bit, except that it is only set, not cleared. However,combined with the timer overflow interrupt that automatically clears the TOV0 flag, thetimer resolution can be increased by software. There are no special cases to consider inthe normal mode, a new counter value can be written anytime.The output compare unit can be used to generate interrupts at some given time. Usingthe output compare to generate waveforms in normal mode is not recommended, sincethis will occupy too much of the CPU time.Clear Timer on CompareMatch (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used tomanipulate the counter resolution.
In CTC mode the counter is cleared to zero when thecounter value (TCNT0) matches the OCR0. The OCR0 defines the top value for thecounter, hence also its resolution. This mode allows greater control of the comparematch output frequency. It also simplifies the operation of counting external events.The timing diagram for the CTC mode is shown in Figure 38.
The counter value(TCNT0) increases until a compare match occurs between TCNT0 and OCR0, and thencounter (TCNT0) is cleared.Figure 38. CTC Mode, Timing DiagramOCn Interrupt Flag SetTCNTnOCn(Toggle)Period(COMn1:0 = 1)1234952467M–AVR–11/04An interrupt can be generated each time the counter value reaches the TOP value byusing the OCF0 flag.
If the interrupt is enabled, the interrupt handler routine can be usedfor updating the TOP value. However, changing the TOP to a value close to BOTTOMwhen the counter is running with none or a low prescaler value must be done with caresince the CTC mode does not have the double buffering feature. If the new value writtento OCR0 is lower than the current value of TCNT0, the counter will miss the comparematch. The counter will then have to count to its maximum value (0xFF) and wraparound starting at 0x00 before the compare match can occur.For generating a waveform output in CTC mode, the OC0 output can be set to toggle itslogical level on each compare match by setting the Compare Output mode bits to Toggle mode (COM01:0 = 1).
The OC0 value will not be visible on the port pin unless thedata direction for the pin is set to output. The waveform generated will have a maximumfrequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequencyis defined by the following equation:f clk_I/Of OCn = ---------------------------------------------2 ⋅ N ⋅ ( 1 + OCRn )The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).As for the normal mode of operation, the TOV0 flag is set in the same timer clock cyclethat the counter counts from MAX to 0x00.Fast PWM ModeThe fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWMoption by its single-slope operation.
The counter counts from BOTTOM to MAX thenrestarts from BOTTOM. In non-inverting Compare Output mode, the output compare(OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match andcleared at BOTTOM. Due to the single-slope operation, the operating frequency of thefast PWM mode can be twice as high as the phase correct PWM mode that uses dualslope operation. This high frequency makes the fast PWM mode well suited for powerregulation, rectification, and DAC applications.
High frequency allows physically smallsized external components (coils, capacitors), and therefore reduces total system cost.In fast PWM mode, the counter is incremented until the counter value matches the MAXvalue. The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 39. The TCNT0 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs.
The small horizontal line marks on the TCNT0slopes represent compare matches between OCR0 and TCNT0.96ATmega1282467M–AVR–11/04ATmega128Figure 39. Fast PWM Mode, Timing DiagramOCRn Interrupt Flag SetOCRn UpdateandTOVn Interrupt Flag SetTCNTnOCn(COMn1:0 = 2)OCn(COMn1:0 = 3)Period1234567The Timer/Counter overflow flag (TOV0) is set each time the counter reaches Max If theinterrupt is enabled, the interrupt handler routine can be used for updating the comparevalue.In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0pin.
Setting the COM01:0 bits to 2 will produce a non-inverted PWM and an invertedPWM output can be generated by setting the COM01:0 to 3 (See Table 54 on page102). The actual OC0 value will only be visible on the port pin if the data direction for theport pin is set as output. The PWM waveform is generated by setting (or clearing) theOC0 Register at the compare match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the counter is cleared (changes fromMAX to BOTTOM).The PWM frequency for the output can be calculated by the following equation:f clk_I/Of OCnPWM = ----------------N ⋅ 256The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).The extreme values for the OCR0 Register represent special cases when generating aPWM waveform output in the fast PWM mode.
If the OCR0 is set equal to BOTTOM, theoutput will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equalto MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.)A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC0 to toggle its logical level on each compare match (COM01:0 = 1).
Thewaveform generated will have a maximum frequency of foc0 = fclk_I/O/2 when OCR0 is setto zero. This feature is similar to the OC0 toggle in CTC mode, except the double bufferfeature of the output compare unit is enabled in the fast PWM mode.972467M–AVR–11/04Phase Correct PWM ModeThe phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correctPWM waveform generation option. The phase correct PWM mode is based on a dualslope operation.
The counter counts repeatedly from BOTTOM to MAX and then fromMAX to BOTTOM. In non-inverting Compare Output mode, the output compare (OC0) iscleared on the compare match between TCNT0 and OCR0 while counting up, and seton the compare match while downcounting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications.The PWM resolution for the phase correct PWM mode is fixed to 8 bits.
In phase correctPWM mode the counter is incremented until the counter value matches Max When thecounter reaches MAX, it changes the count direction. The TCNT0 value will be equal toMAX for one timer clock cycle. The timing diagram for the phase correct PWM mode isshown on Figure 40. The TCNT0 value is in the timing diagram shown as a histogramfor illustrating the dual-slope operation. The diagram includes non-inverted and invertedPWM outputs. The small horizontal line marks on the TCNT0 slopes represent comparematches between OCR0 and TCNT0.Figure 40.
Phase Correct PWM Mode, Timing DiagramOCn Interrupt Flag SetOCRn UpdateTOVn Interrupt Flag SetTCNTnOCn(COMn1:0 = 2)OCn(COMn1:0 = 3)Period123The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counterreaches the BOTTOM value.In phase correct PWM mode, the compare unit allows generation of PWM waveforms onthe OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. Aninverted PWM output can be generated by setting the COM01:0 to 3 (See Table 55 onpage 103). The actual OC0 value will only be visible on the port pin if the data directionfor the port pin is set as output.
The PWM waveform is generated by clearing (or setting)the OC0 Register at the compare match between OCR0 and TCNT0 when the counterincrements, and setting (or clearing) the OC0 Register at compare match between98ATmega1282467M–AVR–11/04ATmega128OCR0 and TCNT0 when the counter decrements.
The PWM frequency for the outputwhen using phase correct PWM can be calculated by the following equation:f clk_I/Of OCnPCPWM = ----------------N ⋅ 510The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).The extreme values for the OCR0 Register represent special cases when generating aPWM waveform output in the phase correct PWM mode. If the OCR0 is set equal toBOTTOM, the output will be continuously low and if set equal to MAX the output will becontinuously high for non-inverted PWM mode.
For inverted PWM the output will havethe opposite logic values.At the very start of Period 2 in Figure 40 OCn has a transition from high to low eventhough there is no Compare Match. The point of this transition is to guarantee symmetryaround BOTTOM. There are two cases that give a transition without Compare Match:Timer/Counter TimingDiagrams•OCR0A changes its value from MAX, like in Figure 40. When the OCR0A value isMAX the OCn pin value is the same as the result of a down-counting CompareMatch. To ensure symmetry around BOTTOM the OCn value at MAX mustcorrespond to the result of an up-counting Compare Match.•The timer starts counting from a higher value than the one in OCR0A, and for thatreason misses the Compare Match and hence the OCn change that would havehappened on the way up.Figure 41 and Figure 42 contain timing data for the Timer/Counter operation. TheTimer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown asa clock enable signal.
The figure shows the count sequence close to the MAX value.Figure 43 and Figure 44 show the same timing data, but with the prescaler enabled. Thefigures illustrate when interrupt flags are set.The following figures show the Timer/Counter in Synchronous mode, and the timer clock(clkT0) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O shouldbe replaced by the Timer/Counter Oscillator clock. The figures include information onwhen interrupt flags are set. Figure 41 contains timing data for basic Timer/Counteroperation. The figure shows the count sequence close to the MAX value in all modesother than phase correct PWM mode.Figure 41.
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