ATmega128 (961723), страница 21
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Timer/Counter Timing Diagram, No PrescalingclkI/OclkTn(clkI/O /1)TCNTnMAX - 1MAXBOTTOMBOTTOM + 1TOVnFigure 42 shows the same timing data, but with the prescaler enabled.992467M–AVR–11/04Figure 42. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnMAX - 1MAXBOTTOMBOTTOM + 1TOVnFigure 43 shows the setting of OCF0 in all modes except CTC mode.Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnOCRnOCRn - 1OCRnOCRn + 1OCRn + 2OCRn ValueOCFnFigure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.100ATmega1282467M–AVR–11/04ATmega128Figure 44.
Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, withPrescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTn(CTC)TOP - 1TOPOCRnBOTTOMBOTTOM + 1TOPOCFn8-bit Timer/CounterRegister DescriptionTimer/Counter ControlRegister – TCCR0Bit76543210FOC0WGM00COM01COM00WGM01CS02CS01CS00Read/WriteWR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TCCR0• Bit 7 – FOC0: Force Output CompareThe FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, forensuring compatibility with future devices, this bit must be set to zero when TCCR0 iswritten when operating in PWM mode.
When writing a logical one to the FOC0 bit, animmediate compare match is forced on the waveform generation unit. The OC0 output ischanged according to its COM01:0 bits setting. Note that the FOC0 bit is implementedas a strobe. Therefore it is the value present in the COM01:0 bits that determines theeffect of the forced compare.A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC modeusing OCR0 as TOP.The FOC0 bit is always read as zero.• Bit 6, 3 – WGM01:0: Waveform Generation ModeThese bits control the counting sequence of the counter, the source for the maximum(TOP) counter value, and what type of waveform generation to be used.
Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Comparematch (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table52 and “Modes of Operation” on page 95.1012467M–AVR–11/04Table 52. Waveform Generation Mode Bit DescriptionModeWGM01(1)(CTC0)WGM00(1)(PWM0)001Timer/CounterMode of OperationTOPUpdate ofOCR0 atTOV0 FlagSet on0Normal0xFFImmediateMAX01PWM, PhaseCorrect0xFFTOPBOTTOM210CTCOCR0ImmediateMAX311Fast PWM0xFFTOPMAXNote:1. The CTC0 and PWM0 bit definition names are now obsolete.
Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible withprevious versions of the timer.• Bit 5:4 – COM01:0: Compare Match Output ModeThese bits control the output compare pin (OC0) behavior. If one or both of theCOM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/Opin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver.When OC0 is connected to the pin, the function of the COM01:0 bits depends on theWGM01:0 bit setting.
Table 53 shows the COM01:0 bit functionality when the WGM01:0bits are set to a normal or CTC mode (non-PWM).Table 53. Compare Output Mode, non-PWM ModeCOM01COM00Description00Normal port operation, OC0 disconnected.01Toggle OC0 on compare match10Clear OC0 on compare match11Set OC0 on compare matchTable 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fastPWM mode.Table 54. Compare Output Mode, Fast PWM Mode(1)COM01COM0000Normal port operation, OC0 disconnected.01Reserved10Clear OC0 on compare match, set OC0 at TOP11Set OC0 on compare match, clear OC0 at TOPNote:Description1. A special case occurs when OCR0 equals TOP and COM01 is set.
In this case, thecompare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode”on page 96 for more details.Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phasecorrect PWM mode.102ATmega1282467M–AVR–11/04ATmega128Table 55. Compare Output Mode, Phase Correct PWM Mode(1)COM01COM0000Normal port operation, OC0 disconnected.01Reserved10Clear OC0 on compare match when up-counting. Set OC0 on comparematch when downcounting.11Set OC0 on compare match when up-counting. Clear OC0 on comparematch when downcounting.Note:Description1. A special case occurs when OCR0 equals TOP and COM01 is set.
In this case, thecompare match is ignored, but the set or clear is done at TOP. See “Phase CorrectPWM Mode” on page 98 for more details.• Bit 2:0 – CS02:0: Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter, seeTable 56.Table 56. Clock Select Bit DescriptionTimer/Counter Register –TCNT0CS02CS01CS00000No clock source (Timer/Counter stopped)001clkT0S/(No prescaling)010clkT0S/8 (From prescaler)011clkT0S/32 (From prescaler)100clkT0S/64 (From prescaler)101clkT0S/128 (From prescaler)110clkT0S/256 (From prescaler)111clkT0S/1024 (From prescaler)Bit76Description543210TCNT0[7:0]TCNT0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The Timer/Counter Register gives direct access, both for read and write operations, tothe Timer/Counter unit 8-bit counter.
Writing to the TCNT0 Register blocks (removes)the compare match on the following timer clock. Modifying the counter (TCNT0) whilethe counter is running, introduces a risk of missing a compare match between TCNT0and the OCR0 Register.Output Compare Register –OCR0Bit76543210OCR0[7:0]OCR0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The Output Compare Register contains an 8-bit value that is continuously comparedwith the counter value (TCNT0).
A match can be used to generate an output compareinterrupt, or to generate a waveform output on the OC0 pin.1032467M–AVR–11/04Asynchronous Operationof the Timer/CounterAsynchronous StatusRegister – ASSRBit76543210––––AS0TCN0UBOCR0UBTCR0UBRead/WriteRRRRR/WRRRInitial Value00000000ASSR• Bit 3 – AS0: Asynchronous Timer/Counter0When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O.
WhenAS0 is written to one, Timer/Counter is clocked from a crystal Oscillator connected tothe Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents ofTCNT0, OCR0, and TCCR0 might be corrupted.• Bit 2 – TCN0UB: Timer/Counter0 Update BusyWhen Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomesset. When TCNT0 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to beupdated with a new value.• Bit 1 – OCR0UB: Output Compare Register0 Update BusyWhen Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomesset.
When OCR0 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that OCR0 is ready to beupdated with a new value.• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update BusyWhen Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomesset. When TCCR0 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to beupdated with a new value.If a write is performed to any of the three Timer/Counter0 Registers while its updatebusy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When readingTCNT0, the actual timer value is read.
When reading OCR0 or TCCR0, the value in thetemporary storage register is read.Asynchronous Operation ofTimer/Counter0When Timer/Counter0 operates asynchronously, some considerations must be taken.•Warning: When switching between asynchronous and synchronous clocking ofTimer/Counter0, the Timer Registers TCNT0, OCR0, and TCCR0 might becorrupted. A safe procedure for switching clock source is:1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0.2.
Select clock source by setting AS0 as appropriate.3. Write new values to TCNT0, OCR0, and TCCR0.4. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, andTCR0UB.5. Clear the Timer/Counter0 interrupt flags.6. Enable interrupts, if needed.104ATmega1282467M–AVR–11/04ATmega128•The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying anexternal clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation.The CPU main clock frequency must be more than four times the Oscillatorfrequency.•When writing to one of the registers TCNT0, OCR0, or TCCR0, the value istransferred to a temporary register, and latched after two positive edges on TOSC1.The user should not write a new value before the contents of the TemporaryRegister have been transferred to its destination.
Each of the three mentionedregisters have their individual temporary register, which means that e.g., writing toTCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to thedestination register has taken place, the Asynchronous Status Register – ASSR hasbeen implemented.•When entering Power-save or Extended Standby mode after having written toTCNT0, OCR0, or TCCR0, the user must wait until the written register has beenupdated if Timer/Counter0 is used to wake up the device. Otherwise, the MCU willenter sleep mode before the changes are effective. This is particularly important ifthe Output Compare0 interrupt is used to wake up the device, since the outputcompare function is disabled during writing to OCR0 or TCNT0.
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