ATmega128 (961723), страница 24
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Counter Unit Block DiagramDATA BUS (8-bit)TOVn(Int.Req.)TEMP (8-bit)Clock SelectCountTCNTnH (8-bit) TCNTnL (8-bit)TCNTn (16-bit Counter)ClearDirectionControl LogicclkTnEdgeDetectorTn( From Prescaler )TOPBOTTOMSignal description (internal signals):CountIncrement or decrement TCNTn by 1.DirectionSelect between increment and decrement.ClearClear TCNTn (set all bits to zero).clkTnTimer/Counter clock.TOPSignalize that TCNTn has reached maximum value.BOTTOMSignalize that TCNTn has reached minimum value (zero).The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High(TCNTnH) containing the upper 8 bits of the counter, and Counter Low (TCNTnL) containing the lower 8 bits.
The TCNTnH Register can only be indirectly accessed by theCPU. When the CPU does an access to the TCNTnH I/O location, the CPU accessesthe high byte Temporary Register (TEMP). The Temporary Register is updated with theTCNTnH value when the TCNTnL is read, and TCNTnH is updated with the TemporaryRegister value when TCNTnL is written.
This allows the CPU to read or write the entire16-bit counter value within one clock cycle via the 8-bit data bus. It is important to noticethat there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sectionswhere they are of importance.Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each Timer Clock (clkTn). The clkTn can be generated from an external orinternal clock source, selected by the Clock Select bits (CSn2:0). When no clock sourceis selected (CSn2:0 = 0) the timer is stopped.
However, the TCNTn value can beaccessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations.The counting sequence is determined by the setting of the Waveform Generation modebits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and1152467M–AVR–11/04TCCRnB). There are close connections between how the counter behaves (counts) andhow waveforms are generated on the output compare outputs OCnx.
For more detailsabout advanced counting sequences and waveform generation, see “Modes of Operation” on page 121.The Timer/Counter Overflow (TOVn) flag is set according to the mode of operationselected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.Input Capture UnitThe Timer/Counter incorporates an Input Capture unit that can capture external eventsand give them a time-stamp indicating time of occurrence. The external signal indicatingan event, or multiple events, can be applied via the ICPn pin or alternatively, for theTimer/Counter1 only, via the Analog Comparator unit.
The time-stamps can then beused to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.The Input Capture unit is illustrated by the block diagram shown in Figure 48. The elements of the block diagram that are not directly a part of the Input Capture unit are grayshaded. The small “n” in register and bit names indicates the Timer/Counter number.Figure 48. Input Capture Unit Block DiagramDATA BUS(8-bit)TEMP (8-bit)ICRnH (8-bit)WRITEICRnL (8-bit)TCNTnH (8-bit)ICRn (16-bit Register)ACO*AnalogComparatorACIC*TCNTnL (8-bit)TCNTn (16-bit Counter)ICNCICESNoiseCancelerEdgeDetectorICFn (Int.Req.)ICPnNote:The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – notTimer/Counter3.When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn),alternatively on the analog Comparator output (ACO), and this change confirms to thesetting of the edge detector, a capture will be triggered.
When a capture is triggered, the16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). TheInput Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copiedinto ICRn Register. If enabled (TICIEn = 1), the Input Capture flag generates an InputCapture interrupt. The ICFn flag is automatically cleared when the interrupt is executed.Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/Obit location.116ATmega1282467M–AVR–11/04ATmega128Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading thelow byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the highbyte is copied into the high byte Temporary Register (TEMP).
When the CPU reads theICRnH I/O location it will access the TEMP Register.The ICRn Register can only be written when using a Waveform Generation mode thatutilizes the ICRn Register for defining the counter’s TOP value. In these cases theWaveform Generation mode (WGMn3:0) bits must be set before the TOP value can bewritten to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL.For more information on how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 112.Input Capture Pin SourceThe main trigger source for the Input Capture unit is the Input Capture Pin (ICPn).Timer/Counter1 can alternatively use the analog comparator output as trigger source forthe Input Capture unit.
The Analog Comparator is selected as trigger source by settingthe analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control andStatus Register (ACSR). Be aware that changing trigger source can trigger a capture.The Input Capture flag must therefore be cleared after the change.Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs aresampled using the same technique as for the Tn pin (Figure 59 on page 142). The edgedetector is also identical.
However, when the noise canceler is enabled, additional logicis inserted before the edge detector, which increases the delay by four system clockcycles. Note that the input of the noise canceler and edge detector is always enabledunless the Timer/Counter is set in a Waveform Generation mode that uses ICRn todefine TOP.An Input Capture can be triggered by software by controlling the port of the ICPn pin.Noise CancelerThe noise canceler improves noise immunity by using a simple digital filtering scheme.The noise canceler input is monitored over four samples, and all four must be equal forchanging the output that in turn is used by the edge detector.The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bitin Timer/Counter Control Register B (TCCRnB).
When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, tothe update of the ICRn Register. The noise canceler uses the system clock and is therefore not affected by the prescaler.Using the Input Capture UnitThe main challenge when using the Input Capture unit is to assign enough processorcapacity for handling the incoming events. The time between two events is critical. If theprocessor has not read the captured value in the ICRn Register before the next eventoccurs, the ICRn will be overwritten with a new value.
In this case the result of the capture will be incorrect.When using the Input Capture interrupt, the ICRn Register should be read as early in theinterrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximumnumber of clock cycles it takes to handle any of the other interrupt requests.Using the Input Capture unit in any mode of operation when the TOP value (resolution)is actively changed during operation, is not recommended.Measurement of an external signal’s duty cycle requires that the trigger edge is changedafter each capture. Changing the edge sensing must be done as early as possible afterthe ICRn Register has been read.
After a change of the edge, the Input Capture flag1172467M–AVR–11/04(ICFn) must be cleared by software (writing a logical one to the I/O bit location). Formeasuring frequency only, the clearing of the ICFn flag is not required (if an interrupthandler is used).Output Compare UnitsThe 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will setthe Output Compare Flag (OCFnx) at the next timer clock cycle.
If enabled (OCIEnx =1), the output compare flag generates an output compare interrupt. The OCFnx flag isautomatically cleared when the interrupt is executed. Alternatively the OCFnx flag canbe cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set bythe Waveform Generation mode (WGMn3:0) bits and Compare Output mode(COMnx1:0) bits. The TOP and BOTTOM signals are used by the waveform generatorfor handling the special cases of the extreme values in some modes of operation (See“Modes of Operation” on page 121.)A special feature of output compare unit A allows it to define the Timer/Counter TOPvalue (i.e., counter resolution). In addition to the counter resolution, the TOP valuedefines the period time for waveforms generated by the waveform generator.Figure 49 shows a block diagram of the output compare unit.
The small “n” in the register and bit names indicates the device number (n = n for Timer/Counter n), and the “x”indicates output compare unit (A/B/C). The elements of the block diagram that are notdirectly a part of the output compare unit are gray shaded.Figure 49. Output Compare Unit, Block DiagramDATABUS(8-bit)TEMP (8-bit)OCRnxH Buf. (8-bit)OCRnxL Buf.
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