ATmega128 (961723), страница 13
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Reset and Interrupt Vectors (Continued)VectorNo.ProgramAddress(2)31SourceInterrupt Definition$003C(3)USART1, RXUSART1, Rx Complete32$003E(3)USART1, UDREUSART1 Data Register Empty33(3)USART1, TXUSART1, Tx Complete(3)$004034$0042TWITwo-wire Serial Interface35$0044(3)SPM READYStore Program Memory ReadyNotes:1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loaderaddress at reset, see “Boot Loader Support – Read-While-Write Self-Programming”on page 275.2.
When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start ofthe Boot Flash section. The address of each interrupt vector will then be address inthis table added to the start address of the boot Flash section.3. The Interrupts on address $0030 - $0044 do not exist in ATmega103 compatibilitymode.Table 24 shows Reset and interrupt vectors placement for the various combinations ofBOOTRST and IVSEL settings. If the program never enables an interrupt source, theinterrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while theinterrupt vectors are in the Boot section or vice versa.Table 24. Reset and Interrupt Vectors PlacementBOOTRSTIVSEL1Note:58Reset AddressInterrupt Vectors Start Address0$0000$000211$0000Boot Reset Address + $000200Boot Reset Address$000201Boot Reset AddressBoot Reset Address + $0002The Boot Reset Address is shown in Table 112 on page 286.
For the BOOTRST fuse “1”means unprogrammed while “0” means programmed.ATmega1282467M–AVR–11/04ATmega128The most typical and general program setup for the Reset and Interrupt VectorAddresses in ATmega128 is:Address LabelsCodeComments$0000jmpRESET; Reset Handler$0002jmpEXT_INT0; IRQ0 Handler$0004jmpEXT_INT1; IRQ1 Handler$0006jmpEXT_INT2; IRQ2 Handler$0008jmpEXT_INT3; IRQ3 Handler$000AjmpEXT_INT4; IRQ4 Handler$000CjmpEXT_INT5; IRQ5 Handler$000EjmpEXT_INT6; IRQ6 Handler$0010jmpEXT_INT7; IRQ7 Handler$0012jmpTIM2_COMP ; Timer2 Compare Handler$0014jmpTIM2_OVF$0016jmpTIM1_CAPT ; Timer1 Capture Handler$0018jmpTIM1_COMPA; Timer1 CompareA Handler$001AjmpTIM1_COMPB; Timer1 CompareB Handler$001CjmpTIM1_OVF$001EjmpTIM0_COMP ; Timer0 Compare Handler$0020jmpTIM0_OVF; Timer0 Overflow Handler$0022jmpSPI_STC; SPI Transfer Complete Handler$0024jmpUSART0_RXC; USART0 RX Complete Handler$0026jmpUSART0_DRE; USART0,UDR Empty Handler$0028jmpUSART0_TXC; USART0 TX Complete Handler$002AjmpADC; ADC Conversion Complete Handler$002CjmpEE_RDY; EEPROM Ready Handler$002EjmpANA_COMP; Analog Comparator Handler$0030jmpTIM1_COMPC; Timer1 CompareC Handler$0032jmpTIM3_CAPT ; Timer3 Capture Handler$0034jmpTIM3_COMPA; Timer3 CompareA Handler$0036jmpTIM3_COMPB; Timer3 CompareB Handler$0038jmpTIM3_COMPC; Timer3 CompareC Handler$003AjmpTIM3_OVF$003CjmpUSART1_RXC; USART1 RX Complete Handler$003EjmpUSART1_DRE; USART1,UDR Empty Handler$0040jmpUSART1_TXC; USART1 TX Complete Handler$0042HandlerjmpTWI; Two-wire Serial Interface Interrupt$0044jmpSPM_RDY; SPM Ready Handler; Timer2 Overflow Handler; Timer1 Overflow Handler; Timer3 Overflow Handler;$0046RESET:ldir16, high(RAMEND); Main program start$0047outSPH,r16; Set stack pointer to top of RAM$0048ldir16, low(RAMEND)$0049$004AoutseiSPL,r16$004B<instr>; Enable interruptsxxx592467M–AVR–11/04............When the BOOTRST fuse is unprogrammed, the Boot section size set to 8K bytes andthe IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the mosttypical and general program setup for the Reset and Interrupt Vector Addresses is:Address LabelsCode$0000CommentsRESET:ldir16,high(RAMEND); Main program start$0001outSPH,r16; Set stack pointer to top of RAM$0002ldir16,low(RAMEND)$0003$0004outseiSPL,r16$0005<instr>; Enable interruptsxxx;.org $F002$F002jmpEXT_INT0; IRQ0 Handler$F004jmpEXT_INT1; IRQ1 Handler.........;$F044jmpSPM_RDY; Store Program Memory Ready HandlerWhen the BOOTRST fuse is programmed and the Boot section size set to 8K bytes, themost typical and general program setup for the Reset and Interrupt Vector Addresses is:AddressLabelsCodeComments.org $0002$0002jmpEXT_INT0; IRQ0 Handler$0004jmpEXT_INT1; IRQ1 Handler.........;$0044jmpSPM_RDY; Store Program Memory Ready Handler;.org $F000$F000RESET: ldir16,high(RAMEND); Main program start$F001outSPH,r16$F002ldir16,low(RAMEND)$F003$F004outseiSPL,r16$F005<instr>; Set stack pointer to top of RAM; Enable interruptsxxxWhen the BOOTRST fuse is programmed, the Boot section size set to 8K bytes and theIVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:AddressLabelsCodeComments;60.org $F000$F000$F002jmpjmpRESETEXT_INT0; Reset handler; IRQ0 Handler$F004jmpEXT_INT1; IRQ1 Handler.........;$F044jmpSPM_RDY ; Store Program Memory Ready Handler$F046RESET: ldi$F047outSPH,r16$F048ldir16,low(RAMEND)r16,high(RAMEND); Main program start; Set stack pointer to top of RAMATmega1282467M–AVR–11/04ATmega128Moving Interrupts BetweenApplication and Boot SpaceMCU Control Register –MCUCR$F049$F04AoutseiSPL,r16$F04B<instr>; Enable interruptsxxxThe General Interrupt Control Register controls the placement of the interrupt vectortable.Bit76543210SRESRW10SESM1SM0SM2IVSELIVCERead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000MCUCR• Bit 1 – IVSEL: Interrupt Vector SelectWhen the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of theFlash memory.
When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the flash. The actual address of the start of the BootFlash section is determined by the BOOTSZ fuses. Refer to the section “Boot LoaderSupport – Read-While-Write Self-Programming” on page 275 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followedto change the IVSEL bit:1. Write the Interrupt Vector Change Enable (IVCE) bit to one.2.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.Interrupts will automatically be disabled while this sequence is executed. Interrupts aredisabled in the cycle IVCE is set, and they remain disabled until after the instructionfollowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for fourcycles. The I-bit in the Status Register is unaffected by the automatic disabling.Note:If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section.
If interruptvectors are placed in the Application section and Boot Lock bit BLB12 is programed,interrupts are disabled while executing from the Boot Loader section. Refer to the section“Boot Loader Support – Read-While-Write Self-Programming” on page 275 for details onBoot Lock bits.612467M–AVR–11/04• Bit 0 – IVCE: Interrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit.
IVCE iscleared by hardware four cycles after it is written or when IVSEL is written. Setting theIVCE bit will disable interrupts, as explained in the IVSEL description above. See CodeExample below.Assembly Code ExampleMove_interrupts:; Enable change of interrupt vectorsldi r16, (1<<IVCE)out MCUCR, r16; Move interrupts to boot flash sectionldi r16, (1<<IVSEL)out MCUCR, r16retC Code Examplevoid Move_interrupts(void){/* Enable change of interrupt vectors */MCUCR = (1<<IVCE);/* Move interrupts to boot flash section */MCUCR = (1<<IVSEL);}62ATmega1282467M–AVR–11/04ATmega128I/O PortsIntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports.
This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. Thesame applies when changing drive value (if configured as output) or enabling/disablingof pull-up resistors (if configured as input). Each output buffer has symmetrical drivecharacteristics with both high sink and source capability.
The pin driver is strong enoughto drive LED displays directly. All port pins have individually selectable pull-up resistorswith a supply-voltage invariant resistance. All I/O pins have protection diodes to bothVCC and Ground as indicated in Figure 29. Refer to “Electrical Characteristics” on page321 for a complete list of parameters.Figure 29. I/O Pin Equivalent SchematicRPULogicPxnCPINSee Figure"General Digital I/O" forDetailsAll registers and bit references in this section are written in general form.
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