ATmega128 (961723), страница 44
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These can be summarized as follows:•When the TWI has finished an operation and expects application response, theTWINT flag is set. The SCL line is pulled low until TWINT is cleared.•When the TWINT flag is set, the user must update all TWI Registers with the valuerelevant for the next TWI bus cycle. As an example, TWDR must be loaded with thevalue to be transmitted in the next bus cycle.•After all TWI Register updates and other pending application software tasks havebeen completed, TWCR is written.
When writing TWCR, the TWINT bit should beset. Writing a one to TWINT clears the flag. The TWI will then commence executingwhatever operation was specified by the TWCR setting.In the following an assembly and C implementation of the example is given. Note thatthe code below assumes that several definitions have been made for example by usinginclude-files.2112467M–AVR–11/04Assembly Code Example1ldi r16,(1<<TWINT)|(1<<TWSTA)|C ExampleTWCR = (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)(1<<TWEN)2out TWCR, r16wait1:r16,TWCRin3andi r16, 0xF8cpi;outTWDR, r16ldi r16, (1<<TWINT) |(1<<TWEN)4out TWCR, r16wait2:r16,TWCRinERROR();5andi r16, 0xF8cpir16, MT_SLA_ACKbrne ERRORldi r16, DATAoutTWDR, r16ldi r16, (1<<TWINT) |(1<<TWEN)6out TWCR, r16wait3:r16,TWCRinTWCR = (1<<TWINT) |(1<<TWEN);7andi r16, 0xF8cpir16, MT_DATA_ACKbrne ERRORldi r16,(1<<TWINT)|(1<<TWEN)|(1<<TWSTO)outNote:212Load SLA_W into TWDR Register.
ClearTWINT bit in TWCR to start transmission ofaddresswhile (!(TWCR & (1<<TWINT)));if ((TWSR & 0xF8) !=MT_SLA_ACK)ERROR();Wait for TWINT flag set. This indicates that theSLA+W has been transmitted, andACK/NACK has been received.Check value of TWI Status Register. Maskprescaler bits. If status different fromMT_SLA_ACK go to ERRORTWDR = DATA;TWCR = (1<<TWINT) |(1<<TWEN);Load DATA into TWDR Register. Clear TWINTbit in TWCR to start transmission of datawhile (!(TWCR & (1<<TWINT)));sbrs r16,TWINTrjmp wait3inr16,TWSRCheck value of TWI Status Register.
Maskprescaler bits. If status different from STARTgo to ERRORTWDR = SLA_W;sbrs r16,TWINTrjmp wait2inr16,TWSRWait for TWINT flag set. This indicates that theSTART condition has been transmittedif ((TWSR & 0xF8) != START)r16, STARTbrne ERRORldi r16, SLA_WSend START conditionwhile (!(TWCR & (1<<TWINT)))sbrs r16,TWINTrjmp wait1inr16,TWSRCommentsif ((TWSR & 0xF8) !=MT_DATA_ACK)ERROR();Wait for TWINT flag set. This indicates that theDATA has been transmitted, and ACK/NACKhas been received.Check value of TWI Status Register. Maskprescaler bits.
If status different fromMT_DATA_ACK go to ERRORTWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWSTO);Transmit STOP conditionTWCR, r16For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced withinstructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.ATmega1282467M–AVR–11/04ATmega128Transmission ModesThe TWI can operate in one of four major modes. These are named Master Transmitter(MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Severalof these modes can be used in the same application.
As an example, the TWI can useMT mode to write data into a TWI EEPROM, MR mode to read the data back from theEEPROM. If other masters are present in the system, some of these might transmit datato the TWI, and then SR mode would be used. It is the application software that decideswhich modes are legal.The following sections describe each of these modes. Possible status codes aredescribed along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations:S: START conditionRs: REPEATED START conditionR: Read bit (high level at SDA)W: Write bit (low level at SDA)A: Acknowledge bit (low level at SDA)A: Not acknowledge bit (high level at SDA)Data: 8-bit data byteP: STOP conditionSLA: Slave AddressIn Figure 97 to Figure 103, circles are used to indicate that the TWINT flag is set.
Thenumbers in the circles show the status code held in TWSR, with the prescaler bitsmasked to zero. At these points, actions must be taken by the application to continue orcomplete the TWI transfer. The TWI transfer is suspended until the TWINT flag iscleared by software.When the TWINT flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of thefollowing serial transfer are given in Table 88 to Table 91.
Note that the prescaler bitsare masked to zero in these tables.Master Transmitter ModeIn the Master Transmitter mode, a number of data bytes are transmitted to a slavereceiver (see Figure 96). In order to enter a Master mode, a START condition must betransmitted. The format of the following address packet determines whether MasterTransmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MTmode is entered, if SLA+R is transmitted, MR mode is entered. All the status codesmentioned in this section assume that the prescaler bits are zero or are masked to zero.2132467M–AVR–11/04Figure 96.
Data Transfer in Master Transmitter ModeVCCDevice 1Device 2MASTERTRANSMITTERSLAVERECEIVERDevice 3........Device nR1R2SDASCLA START condition is sent by writing the following value to TWCR:TWCRvalueTWINTTWEATWSTATWSTOTWWCTWEN–TWIE1X10X10XTWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written toone to transmit a START condition and TWINT must be written to one to clear theTWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted,the TWINT flag is set by hardware, and the status code in TWSR will be $08 (See Table88).
In order to enter MT mode, SLA+W must be transmitted. This is done by writingSLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) tocontinue the transfer. This is accomplished by writing the following value to TWCR:TWCRvalueTWINTTWEATWSTATWSTOTWWCTWEN–TWIE1X00X10XWhen SLA+W have been transmitted and an acknowledgment bit has been received,TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are $18, $20, or $38. The appropriate action to be taken foreach of these status codes is detailed in Table 88.When SLA+W has been successfully transmitted, a data packet should be transmitted.This is done by writing the data byte to TWDR.
TWDR must only be written whenTWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC)will be set in the TWCR Register. After updating TWDR, the TWINT bit should becleared (by writing it to one) to continue the transfer. This is accomplished by writing thefollowing value to TWCR:TWCRvalueTWINTTWEATWSTATWSTOTWWCTWEN–TWIE1X00X10XThis scheme is repeated until the last byte has been sent and the transfer is ended bygenerating a STOP condition or a repeated START condition.
A STOP condition is generated by writing the following value to TWCR:TWCRvalueTWINTTWEATWSTATWSTOTWWCTWEN–TWIE1X01X10XA REPEATED START condition is generated by writing the following value to TWCR:TWCRvalue214TWINTTWEATWSTATWSTOTWWCTWEN–TWIE1X10X10XATmega1282467M–AVR–11/04ATmega128After a repeated START condition (state $10) the Two-wire Serial Interface can accessthe same slave again, or a new slave without transmitting a STOP condition. RepeatedSTART enables the master to switch between slaves, Master Transmitter mode andMaster Receiver mode without losing control of the bus.Table 88. Status Codes for Master Transmitter ModeStatus Code(TWSR)Prescaler Bitsare 0Application Software ResponseStatus of the Two-wire SerialBus and Two-wire Serial Interface HardwareTo TWCRTo/from TWDRSTASTOTWINTTWEA$08A START condition has beentransmittedLoad SLA+W001XSLA+W will be transmitted;ACK or NOT ACK will be received$10A repeated START conditionhas been transmittedLoad SLA+W or001XLoad SLA+R001XSLA+W will be transmitted;ACK or NOT ACK will be receivedSLA+R will be transmitted;Logic will switch to master receiver modeLoad data byte or001XNo TWDR action orNo TWDR action or100111XXNo TWDR action111XLoad data byte or001XNo TWDR action orNo TWDR action or100111XXNo TWDR action111XLoad data byte or001XNo TWDR action orNo TWDR action or100111XXNo TWDR action111XLoad data byte or001XNo TWDR action orNo TWDR action or100111XXNo TWDR action111XNo TWDR action or001XNo TWDR action101X$18$20$28$30$38SLA+W has been transmitted;ACK has been receivedSLA+W has been transmitted;NOT ACK has been receivedData byte has been transmitted;ACK has been receivedData byte has been transmitted;NOT ACK has been receivedArbitration lost in SLA+W or databytesNext Action Taken by TWI HardwareData byte will be transmitted and ACK or NOT ACK willbe receivedRepeated START will be transmittedSTOP condition will be transmitted andTWSTO flag will be resetSTOP condition followed by a START condition will betransmitted and TWSTO flag will be resetData byte will be transmitted and ACK or NOT ACK willbe receivedRepeated START will be transmittedSTOP condition will be transmitted andTWSTO flag will be resetSTOP condition followed by a START condition will betransmitted and TWSTO flag will be resetData byte will be transmitted and ACK or NOT ACK willbe receivedRepeated START will be transmittedSTOP condition will be transmitted andTWSTO flag will be resetSTOP condition followed by a START condition will betransmitted and TWSTO flag will be resetData byte will be transmitted and ACK or NOT ACK willbe receivedRepeated START will be transmittedSTOP condition will be transmitted andTWSTO flag will be resetSTOP condition followed by a START condition will betransmitted and TWSTO flag will be resetTwo-wire Serial Bus will be released and not addressedslave mode enteredA START condition will be transmitted when the bus becomes free2152467M–AVR–11/04Figure 97.
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