ATmega128 (961723), страница 49
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Once a differentialchannel has been selected, the gain stage may take as much as 125 µs to stabilize tothe new value. Thus conversions should not be started within the first 125 µs afterselecting a new differential channel. Alternatively, conversion results obtained within thisperiod should be discarded.The same settling time should be observed for the first differential conversion afterchanging ADC reference (by changing the REFS1:0 bits in ADMUX).If the JTAG Interface is enabled, the function of ADC channels on PORTF7:4 is overridden.
Refer to Table 42, “Port F Pins Alternate Functions,” on page 80.236ATmega1282467M–AVR–11/04ATmega128ADC Input ChannelsWhen changing channel selections, the user should observe the following guidelines toensure that the correct channel is selected:In Single Conversion mode, always select the channel before starting the conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the conversion to complete before changingthe channel selection.In Free Running mode, always select the channel before starting the first conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the first conversion to complete, and thenchange the channel selection.
Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversionswill reflect the new channel selection.When switching to a differential gain channel, the first conversion result may have apoor accuracy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result.ADC Voltage ReferenceThe reference voltage for the ADC (VREF) indicates the conversion range for the ADC.Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can beselected as either AVCC, internal 2.56V reference, or external AREF pin.AVCC is connected to the ADC through a passive switch.
The internal 2.56V referenceis generated from the internal bandgap reference (VBG) through an internal amplifier. Ineither case, the external AREF pin is directly connected to the ADC, and the referencevoltage can be made more immune to noise by connecting a capacitor between theAREF pin and ground. VREF can also be measured at the AREF pin with a high impedantvoltmeter. Note that VREF is a high impedant source, and only a capacitive load shouldbe connected in a system.If the user has a fixed voltage source connected to the AREF pin, the user may not usethe other reference voltage options in the application, as they will be shorted to theexternal voltage.
If no external voltage is applied to the AREF pin, the user may switchbetween AVCC and 2.56 V as reference selection. The first ADC conversion result afterswitching reference voltage source may be inaccurate, and the user is advised to discard this result.If differential channels are used, the selected reference should not be closer to AVCCthan indicated in Table 136 on page 328.ADC Noise CancelerThe ADC features a noise canceler that enables conversion during sleep mode toreduce noise induced from the CPU core and other I/O peripherals. The noise cancelercan be used with ADC Noise Reduction and Idle mode. To make use of this feature, thefollowing procedure should be used:1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interruptmust be enabled.2.
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.3. If no other interrupts occur before the ADC conversion completes, the ADCinterrupt will wake up the CPU and execute the ADC Conversion Completeinterrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC ConversionComplete interrupt request will be generated when the ADC conversion2372467M–AVR–11/04completes. The CPU will remain in active mode until a new sleep commandis executed.Note that the ADC will not be automatically turned off when entering other sleep modesthan Idle mode and ADC Noise Reduction mode.
The user is advised to write zero toADEN before entering such sleep modes to avoid excessive power consumption. If theADC is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the ADC off and on after waking up from sleep toprompt an extended conversion to get a valid result.Analog Input CircuitryThe Analog Input circuitry for single ended channels is illustrated in Figure 113. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of thatpin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance(combined resistance in the input path).The ADC is optimized for analog signals with an output impedance of approximately10 kΩ or less.
If such a source is used, the sampling time will be negligible. If a sourcewith higher impedance is used, the sampling time will depend on how long time thesource needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since thisminimizes the required charge transfer to the S/H capacitor.If differential gain channels are used, the input circuitry looks somewhat different,although source impedances of a few hundred kΩ or less is recommended.Signal components higher than the Nyquist frequency (fADC / 2) should not be presentfor either kind of channels, to avoid distortion from unpredictable signal convolution. Theuser is advised to remove high frequency components with a low-pass filter beforeapplying the signals as inputs to the ADC.Figure 113.
Analog Input CircuitryIIHADCn1..100 kΩCS/H= 14 pFIILVCC/2Analog Noise CancelingTechniquesDigital circuitry inside and outside the device generates EMI which might affect theaccuracy of analog measurements. If conversion accuracy is critical, the noise level canbe reduced by applying the following techniques:1. Keep analog signal paths as short as possible. Make sure analog tracks runover the ground plane, and keep them well away from high-speed switchingdigital tracks.2.
The AVCC pin on the device should be connected to the digital VCC supplyvoltage via an LC network as shown in Figure 114.3. Use the ADC noise canceler function to reduce induced noise from the CPU.238ATmega1282467M–AVR–11/04ATmega1284. If any ADC port pins are used as digital outputs, it is essential that these donot switch while a conversion is in progress.Figure 114. ADC Power Connections(AD0) PA0VCC10µΗ52GND53(ADC7) PF754(ADC6) PF655(ADC5) PF556(ADC4) PF457(ADC3) PF358(ADC2) PF259(ADC1) PF160(ADC0) PF061AREF62GNDAVCC63641PEN100nF51Offset CompensationSchemesThe gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible.
The remaining offset in the analog path can bemeasured directly by selecting the same channel for both differential inputs. This offsetresidue can be then subtracted in software from the measurement results. Using thiskind of software based offset correction, offset on any channel can be reduced belowone LSB.2392467M–AVR–11/04ADC Accuracy DefinitionsAn n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2nsteps (LSBs).
The lowest code is read as 0, and the highest code is read as 2n-1.Several parameters describe the deviation from the ideal behavior:•Offset: The deviation of the first transition (0x000 to 0x001) compared to the idealtransition (at 0.5 LSB). Ideal value: 0 LSB.Figure 115. Offset ErrorOutput CodeIdeal ADCActual ADCOffsetError•VREF Input VoltageGain Error: After adjusting for offset, the gain error is found as the deviation of thelast transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB belowmaximum). Ideal value: 0 LSBFigure 116.
Gain ErrorOutput CodeGainErrorIdeal ADCActual ADCVREF Input Voltage•240Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is themaximum deviation of an actual transition compared to an ideal transition for anycode. Ideal value: 0 LSB.ATmega1282467M–AVR–11/04ATmega128Figure 117. Integral Non-linearity (INL)Output CodeINLIdeal ADCActual ADCVREF•Input VoltageDifferential Non-linearity (DNL): The maximum deviation of the actual code width(the interval between two adjacent transitions) from the ideal code width (1 LSB).Ideal value: 0 LSB.Figure 118. Differential Non-linearity (DNL)Output Code0x3FF1 LSBDNL0x0000VREF Input Voltage•Quantization Error: Due to the quantization of the input voltage into a finite numberof codes, a range of input voltages (1 LSB wide) will code to the same value.
Always±0.5 LSB.•Absolute Accuracy: The maximum deviation of an actual (unadjusted) transitioncompared to an ideal transition for any code. This is the compound effect of offset,gain error, differential error, non-linearity, and quantization error. Ideal value: ±0.5LSB.2412467M–AVR–11/04ADC Conversion ResultAfter the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Result Registers (ADCL, ADCH).For single ended conversion, the result isV IN ⋅ 1024ADC = -------------------------V REFwhere VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 97 on page 244 and Table 98 on page 244).
0x000 represents ground,and 0x3FF represents the selected reference voltage minus one LSB.If differential channels are used, the result is( V POS – V NEG ) ⋅ GAIN ⋅ 512ADC = ----------------------------------------------------------------------V REFwhere VPOS is the voltage on the positive input pin, VNEG the voltage on the negativeinput pin, GAIN the selected gain factor, and VREF the selected voltage reference.
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