ATmega128 (961723), страница 56
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Alternatively theRWWSB bit will automatically be cleared if a page load operation is initiated.• Bit 5 – Res: Reserved BitThis bit is a reserved bit in the ATmega128 and always read as zero.• Bit 4 – RWWSRE: Read-While-Write Section Read EnableWhen Programming (page erase or page write) to the RWW section, the RWW sectionis blocked for reading (the RWWSB will be set by hardware). To re-enable the RWWsection, the user software must wait until the programming is completed (SPMEN will becleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, thenext SPM instruction within four clock cycles re-enables the RWW section. The RWWsection cannot be re-enabled while the Flash is busy with a page erase or a page write(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flashload operation will abort and the data loaded will be lost.• Bit 3 – BLBSET: Boot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles sets Boot Lock bits, according to the data in R0.
The data in R1 andthe address in the Z-pointer are ignored. The BLBSET bit will automatically be clearedupon completion of the lock bit set, or if no SPM instruction is executed within four clockcycles.An LPM instruction within three cycles after BLBSET and SPMEN are set in theSPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 inthe Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits fromSoftware” on page 283 for details.• Bit 2 – PGWRT: Page WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes page write, with the data stored in the temporary buffer.
Thepage address is taken from the high part of the Z-pointer. The data in R1 and R0 areignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPMinstruction is executed within four clock cycles. The CPU is halted during the entire pagewrite operation if the NRWW section is addressed.• Bit 1 – PGERS: Page EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes page erase. The page address is taken from the high part of2792467M–AVR–11/04the Z-pointer. The data in R1 and R0 are ignored.
The PGERS bit will auto-clear uponcompletion of a page erase, or if no SPM instruction is executed within four clock cycles.The CPU is halted during the entire page write operation if the NRWW section isaddressed.• Bit 0 – SPMEN: Store Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to onetogether with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPMinstruction will have a special meaning, see description above.
If only SPMEN is written,the following SPM instruction will store the value in R1:R0 in the temporary page bufferaddressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit willauto-clear upon completion of an SPM instruction, or if no SPM instruction is executedwithin four clock cycles. During page erase and page write, the SPMEN bit remains highuntil the operation is completed.Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in thelower five bits will have no effect.Addressing the FlashDuring SelfProgrammingThe Z-pointer together with RAMPZ are used to address the SPM commands.
Fordetails on how to use the RAMPZ, see “RAM Page Z Select Register – RAMPZ” onpage 12.15141312111098ZH (R31)BitZ15Z14Z13Z12Z11Z10Z9Z8ZL (R30)Z7Z6Z5Z4Z3Z2Z1Z076543210Since the Flash is organized in pages (see Table 123 on page 293), the programcounter can be treated as having two different sections. One section, consisting of theleast significant bits, is addressing the words within a page, while the most significantbits are addressing the pages.
This is shown in Figure 134. Note that the page eraseand page write operations are addressed independently. Therefore it is of major importance that the Boot Loader software addresses the same page in both the page eraseand page write operation. Once a programming operation is initiated, the address islatched and the Z-pointer/RAMPZ can be used for other operations.The only SPM operation that does not use the Z-pointer/RAMPZ is setting the BootLoader Lock bits. The content of the Z-pointer/RAMPZ is ignored and will have no effecton the operation.
The (E)LPM instruction does also use the Z-pointer/RAMPZ to storethe address. Since this instruction addresses the Flash byte by byte, also the LSB (bitZ0) of the Z-pointer is used.280ATmega1282467M–AVR–11/04ATmega128Figure 134. Addressing the Flash During SPM(1)BIT 15 ZPCMSBRAMPZZPAGEMSB1 00PCMSBPROGRAMCOUNTERZ - REGISTERPAGEMSBPCPAGEPAGE ADDRESSWITHIN THE FLASHPCWORDWORD ADDRESSWITHIN A PAGEPROGRAM MEMORYPAGEPAGEINSTRUCTION WORDPCWORD[PAGEMSB:0]:000102PAGEENDNotes:Self-Programming theFlash1. The different variables used in Figure 134 are listed in Table 114 on page 287.2. PCPAGE and PCWORD are listed in Table 124 on page 293.The program memory is updated in a page by page fashion.
Before programming apage with the data stored in the temporary page buffer, the page must be erased. Thetemporary page buffer is filled one word at a time using SPM and the buffer can be filledeither before the page erase command or between a page erase and a page writeoperation:Alternative 1, fill the buffer before a page erase•Fill temporary page buffer•Perform a page erase•Perform a page writeAlternative 2, fill the buffer after page erase•Perform a page erase•Fill temporary page buffer•Perform a page writeIf only a part of the page needs to be changed, the rest of the page must be stored (forexample in the temporary page buffer) before the erase, and then be rewritten.
Whenusing alternative 1, the Boot Loader provides an effective Read-Modify-Write featurewhich allows the user software to first read the page, do the necessary changes, andthen write back the modified data. If alternative 2 is used, it is not possible to read theold data while loading since the page is already erased. The temporary page buffer canbe accessed in a random sequence. It is essential that the page address used in boththe page erase and page write operation is addressing the same page. See “SimpleAssembly Code Example for a Boot Loader” on page 284 for an assembly codeexample.2812467M–AVR–11/04Performing Page Erase bySPMFilling the Temporary Buffer(Page Loading)To execute page erase, set up the address in the Z-pointer and RAMPZ, write“X0000011” to SPMCSR and execute SPM within four clock cycles after writingSPMCSR.
The data in R1 and R0 is ignored. The page address must be written toPCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during thisoperation.•Page Erase to the RWW section: The NRWW section can be read during the pageerase.•Page Erase to the NRWW section: The CPU is halted during the operation.To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write“00000001” to SPMCSR and execute SPM within four clock cycles after writingSPMCSR. The content of PCWORD in the Z-register is used to address the data in thetemporary buffer. The temporary buffer will auto-erase after a page write operation or bywriting the RWWSRE bit in SPMCSR.
It is also erased after a System Reset. Note that itis not possible to write more than one time to each address without erasing the temporary buffer.Note:Performing a Page WriteIf the EEPROM is written in the middle of an SPM Page Load operation, all data loadedwill be lost.To execute page write, set up the address in the Z-pointer and RAMPZ, write“X0000101” to SPMCSR and execute SPM within four clock cycles after writingSPMCSR. The data in R1 and R0 is ignored.
The page address must be written toPCPAGE. Other bits in the Z-pointer must be written zero during this operation.•Page Write to the RWW section: The NRWW section can be read during the pagewrite.•Page Write to the NRWW section: The CPU is halted during the operation.Using the SPM InterruptIf the SPM interrupt is enabled, the SPM interrupt will generate a constant interruptwhen the SPMEN bit in SPMCSR is cleared.
This means that the interrupt can be usedinstead of polling the SPMCSR Register in software. When using the SPM interrupt, theinterrupt vectors should be moved to the BLS section to avoid that an interrupt isaccessing the RWW section when it is blocked for reading. How to move the interruptsis described in “Interrupts” on page 57.Consideration While UpdatingBLSSpecial care must be taken if the user allows the Boot Loader section to be updated byleaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself cancorrupt the entire Boot Loader, and further software updates might be impossible.
If it isnot necessary to change the Boot Loader software itself, it is recommended to programthe Boot Lock bit11 to protect the Boot Loader software from any internal softwarechanges.Prevent Reading the RWWSection During SelfProgrammingDuring Self-Programming (either page erase or page write), the RWW section is alwaysblocked for reading. The user software itself must prevent that this section is addressedduring the Self-Programming operation.
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