ATmega128 (961723), страница 58
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Boot Size ConfigurationBootSizeBootLoaderFlashSectionEndApplicationsectionBOOTSZ1BOOTSZ011512words4$0000 $FDFF$FE00 $FFFF$FDFF$FE00101024words8$0000 $FBFF$FC00 $FFFF$FBFF$FC00012048words16$0000 $F7FF$F800 $FFFF$F7FF$F800004096words32$0000 $EFFF$F000 $FFFF$EFFF$F000Note:PagesApplicationFlashSectionBootResetAddress(start BootLoaderSection)The different BOOTSZ fuse configurations are shown in Figure 133Table 113. Read-While-Write Limit(1)SectionAddressRead-While-Write section (RWW)480$0000 - $EFFFNo Read-While-Write section (NRWW)32$F000 - $FFFFNote:286Pages1. For details about these two section, see “No Read-While-Write Section – NRWW” onpage 276 and “Read-While-Write Section – RWW” on page 276ATmega1282467M–AVR–11/04ATmega128Table 114. Explanation of Different Variables Used in Figure 134 and the Mapping tothe Z-Pointer(3)CorrespondingZ-valueVariablePCMSB15Most significant bit in the program counter.
(Theprogram counter is 16 bits PC[15:0])6Most significant bit which is used to address thewords within one page (128 words in a pagerequires 7 bits PC [6:0]).PAGEMSBZ16(1)Bit in Z-register that is mapped to PCMSB.Because Z0 is not used, the ZPCMSB equalsPCMSB + 1.Z7Bit in Z-register that is mapped to PAGEMSB.Because Z0 is not used, the ZPAGEMSBequals PAGEMSB + 1.ZPCMSBZPAGEMSBPCPAGEPCWORDNotes:Description(2)PC[15:7]Z16(1):Z8Program counter page address: Page select, forpage erase and page writePC[6:0]Z7:Z1Program counter word address: Word select, forfilling temporary buffer (must be zero duringpage write operation)1. The Z-register is only 16 bits wide.
Bit 16 is located in the RAMPZ register in the I/Omap.2. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.3. See “Addressing the Flash During Self-Programming” on page 280 for details aboutthe use of Z-pointer during self-programming.2872467M–AVR–11/04MemoryProgrammingProgram and DataMemory Lock BitsThe ATmega128 provides six Lock bits which can be left unprogrammed (“1”) or can beprogrammed (“0”) to obtain the additional features listed in Table 116.
The Lock bits canonly be erased to “1” with the Chip Erase command.Table 115. Lock Bit ByteLock Bit ByteDescriptionDefault Value7–1 (unprogrammed)6–1 (unprogrammed)BLB125Boot lock bit1 (unprogrammed)BLB114Boot lock bit1 (unprogrammed)BLB023Boot lock bit1 (unprogrammed)BLB012Boot lock bit1 (unprogrammed)LB21Lock bit1 (unprogrammed)LB10Lock bit1 (unprogrammed)Note:Bit No.“1” means unprogrammed, “0´means programmedTable 116. Lock Bit Protection ModesMemory Lock BitsLB modeLB2LB1111No memory lock features enabled.0Further programming of the Flash and EEPROM isdisabled in Parallel and SPI/JTAG Serial Programmingmode.
The Fuse bits are locked in both Serial and ParallelProgramming mode.(1)Further programming and verification of the Flash andEEPROM is disabled in Parallel and SPI/JTAG SerialProgramming mode. The Fuse bits are locked in bothSerial and Parallel Programming mode.(1)21300BLB0 modeBLB02BLB01111No restrictions for SPM or (E)LPM accessing theApplication section.210SPM is not allowed to write to the Application section.0SPM is not allowed to write to the Application section, and(E)LPM executing from the Boot Loader section is notallowed to read from the Application section. If interruptvectors are placed in the Boot Loader section, interruptsare disabled while executing from the Application section.(E)LPM executing from the Boot Loader section is notallowed to read from the Application section.
If interruptvectors are placed in the Boot Loader section, interruptsare disabled while executing from the Application section.3288Protection Type0401BLB1 modeBLB12BLB11ATmega1282467M–AVR–11/04ATmega128Table 116. Lock Bit Protection Modes (Continued)Memory Lock Bits111No restrictions for SPM or (E)LPM accessing the BootLoader section.210SPM is not allowed to write to the Boot Loader section.0SPM is not allowed to write to the Boot Loader section,and (E)LPM executing from the Application section is notallowed to read from the Boot Loader section.
If interruptvectors are placed in the Application section, interruptsare disabled while executing from the Boot Loader section.1(E)LPM executing from the Application section is notallowed to read from the Boot Loader section. If interruptvectors are placed in the Application section, interruptsare disabled while executing from the Boot Loader section.3040Notes:Fuse BitsProtection Type1. Program the fuse bits before programming the Lock bits.2. “1” means unprogrammed, “0´means programmedThe ATmega128 has three fuse bytes. Table 117 - Table 119 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes.
Note that thefuses are read as logical zero, “0”, if they are programmed.Table 117. Extended Fuse ByteExtended Fuse ByteBit No.DescriptionDefault Value–7–1–6–1–5–1–4–1–3–12–1M103C1ATmega103 compatibility mode0 (programmed)WDTON(2)0Watchdog Timer always on1 (unprogrammed)–(1)Notes:1. See “ATmega103 and ATmega128 Compatibility” on page 4 for details.2. See “Watchdog Timer Control Register – WDTCR” on page 53 for details.2892467M–AVR–11/04Table 118. Fuse High ByteFuse HighByteBit No.DescriptionDefault Value(4)OCDEN7Enable OCD1 (unprogrammed, OCDdisabled)JTAGEN(5)6Enable JTAG0 (programmed, JTAG enabled)5Enable Serial Program andData Downloading0 (programmed, SPI prog.enabled)CKOPT(2)4Oscillator options1 (unprogrammed)EESAVE3EEPROM memory is preservedthrough the Chip Erase1 (unprogrammed, EEPROM notpreserved)BOOTSZ12Select Boot Size (see Table 112for details)0 (programmed)(3)BOOTSZ01Select Boot Size (see Table 112for details)0 (programmed)(3)BOOTRST0Select Reset Vector1 (unprogrammed)SPIENNotes:(1)1.
The SPIEN fuse is not accessible in SPI Serial Programming mode.2. The CKOPT fuse functionality depends on the setting of the CKSEL bits. See “ClockSources” on page 35 for details.3. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 112 onpage 2864. Never ship a product with the OCDEN Fuse programmed regardless of the setting oflock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts ofthe clock system to be running in all sleep modes.
This may increase the powerconsumption.5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This to avoid static current at the TDO pin in the JTAG interface.Table 119. Fuse Low ByteFuse LowByteBit No.DescriptionDefault ValueBODLEVEL7Brown out detector trigger level1 (unprogrammed)BODEN6Brown out detector enable1 (unprogrammed, BOD disabled)SUT15Select start-up time1 (unprogrammed)(1)SUT04Select start-up time0 (programmed)(1)CKSEL33Select Clock source0 (programmed)(2)CKSEL22Select Clock source0 (programmed)(2)CKSEL11Select Clock source0 (programmed)(2)CKSEL00Select Clock source1 (unprogrammed)(2)Notes:1.
The default value of SUT1..0 results in maximum start-up time. See Table 14 on page39 for details.2. The default setting of CKSEL3..0 results in Internal RC Oscillator @ 1 MHz. SeeTable 6 on page 35 for details.The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits arelocked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming theLock bits.290ATmega1282467M–AVR–11/04ATmega128Latching of FusesThe Fuse values are latched when the device enters Programming mode and changesof the fuse values will have no effect until the part leaves Programming mode.
This doesnot apply to the EESAVE fuse which will take effect once it is programmed. The fusesare also latched on power-up in normal mode.Signature BytesAll Atmel microcontrollers have a three-byte signature code which identifies the device.This code can be read in both serial and parallel mode, also when the device is locked.The three bytes reside in a separate address space.For the ATmega128 the signature bytes are:1.
$000: $1E (indicates manufactured by Atmel)2. $001: $97 (indicates 128KB Flash memory)3. $002: $02 (indicates ATmega128 device when $001 is $97)Calibration ByteThe ATmega128 stores four different calibration values for the internal RC Oscillator.These bytes resides in the signature row high byte of the addresses 0x000, 0x0001,0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz valueis automatically loaded into the OSCCAL Register. If other frequencies are used, thecalibration value has to be loaded manually, see “Oscillator Calibration Register – OSCCAL” on page 39 for details.2912467M–AVR–11/04Parallel ProgrammingParameters, PinMapping, andCommandsThis section describes how to parallel program and verify Flash Program memory,EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega128.
Pulsesare assumed to be at least 250 ns unless otherwise noted.Signal NamesIn this section, some pins of the ATmega128 are referenced by signal names describingtheir functionality during parallel programming, see Figure 135 and Table 120. Pins notdescribed in the following table are referenced by pin names.The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 122.When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 123.Figure 135.
Parallel Programming+5VRDY/BSYPD1OEPD2WRPD3BS1PD4XA0PD5XA1PD6PAGELPD7+12 VVCC+5VAVCCPB7 - PB0DATARESETBS2PA0XTAL1GNDTable 120. Pin Name MappingSignal Name inProgramming ModePin NameI/OFunctionPD1O0: Device is busy programming, 1: Device is readyfor new commandOEPD2IOutput Enable (Active low)WRPD3IWrite Pulse (Active low)PD4IByte Select 1 (“0” selects low byte, “1” selects highbyte)XA0PD5IXTAL Action Bit 0XA1PD6IXTAL Action Bit 1RDY/BSYBS1292ATmega1282467M–AVR–11/04ATmega128Table 120. Pin Name Mapping (Continued)Signal Name inProgramming ModePAGELBS2DATAPin NameI/OFunctionPD7IProgram Memory and EEPROM data Page LoadPA0IByte Select 2 (“0” selects low byte, “1” selects 2’ndhigh byte)PB7-0I/OBi-directional Data bus (Output when OE is low)Table 121.
Pin Values Used to Enter Programming ModePinSymbolValuePAGELProg_enable[3]0XA1Prog_enable[2]0XA0Prog_enable[1]0BS1Prog_enable[0]0Table 122. XA1 and XA0 CodingXA1XA0Action when XTAL1 is Pulsed00Load Flash or EEPROM Address (High or low address byte determined by BS1)01Load Data (High or Low data byte for Flash determined by BS1)10Load Command11No Action, IdleTable 123. Command Byte Bit CodingCommand ByteCommand Executed1000 0000Chip Erase0100 0000Write Fuse bits0010 0000Write Lock bits0001 0000Write Flash0001 0001Write EEPROM0000 1000Read Signature Bytes and Calibration byte0000 0100Read Fuse and Lock bits0000 0010Read Flash0000 0011Read EEPROMTable 124. No. of Words in a Page and no. of Pages in the FlashFlash SizePage SizePCWORDNo.
of PagesPCPAGEPCMSB64K words (128K bytes)128 wordsPC[6:0]512PC[15:7]152932467M–AVR–11/04Table 125. No. of Words in a Page and no. of Pages in the EEPROMEEPROM SizePage SizePCWORDNo. of PagesPCPAGEEEAMSB4K bytes8 bytesEEA[2:0]512EEA[11:3]8Parallel ProgrammingEnter Programming ModeThe following algorithm puts the device in parallel programming mode:1.
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