ATmega128 (961723), страница 61
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“0” = programmed, “1” =unprogrammed. See Table 119 on page290 for details.Read ExtendendFuse bits0101 00000000 1000xxxx xxxxoooo ooooRead Extended Fuse bits. “0” = pro-grammed,“1” = unprogrammed. See Table 119 onpage 290 for details.Read Fuse High Bits0101 10000000 1000xxxx xxxxoooo ooooRead Fuse high bits. “0” = pro-grammed, “1” =unprogrammed. See Table 118 on page290 for details.Read Calibration Byte0011 1000xxxx xxxx0000 00bboooo ooooRead Calibration Byte o at address b.Note:OperationRead H (high or low) data o from Programmemory at word address a:b.Write H (high or low) data i to ProgramMemory page at word address b.
Data lowbyte must be loaded before data high byte isapplied within the same address.Write Program Memory Page at address a:b.Read data o from EEPROM memory ataddress a:b.Write data i to EEPROM memory at addressa:b.Read Lock bits. “0” = programmed, “1” =unprogrammed. See Table 115 on page288 for details.Write Lock bits. Set bits = “0” to program Lockbits.
See Table 115 on page 288 for details.Read Signature Byte o at address b.a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High Byteo = data outi = data inx = don’t care3072467M–AVR–11/04SPI Serial ProgrammingCharacteristicsFor characteristics of the SPI module, see “SPI Timing Characteristics” on page 325.Programming Via theJTAG InterfaceProgramming through the JTAG interface requires control of the four JTAG specificpins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required.To be able to use the JTAG interface, the JTAGEN fuse must be programmed. Thedevice is default shipped with the Fuse programmed. In addition, the JTD bit inMCUCSR must be cleared.
Alternatively, if the JTD bit is set, the external reset can beforced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pinsare available for programming. This provides a means of using the JTAG pins as normalport pins in running mode while still allowing In-System Programming via the JTAGinterface. Note that this technique can not be used when using the JTAG pins forBoundary-scan or On-chip Debug.
In these cases the JTAG pins must be dedicated forthis purpose.As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.Programming Specific JTAGInstructionsThe instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for Programming are listed below.The OPCODE for each instruction is shown behind the instruction name in hex format.The text describes which data register is selected as path between TDI and TDO foreach instruction.The Run-Test/Idle state of the TAP controller is used to generate internal clocks.
It canalso be used as an idle state between JTAG sequences. The state machine sequencefor changing the instruction word is shown in Figure 146.308ATmega1282467M–AVR–11/04ATmega128Figure 146. State Machine Sequence for Changing the Instruction Word1Test-Logic-Reset00Run-Test/Idle1Select-DR Scan1Select-IR Scan0011Capture-DRCapture-IR000Shift-DR11Exit1-DR00Pause-DR0Pause-IR110Exit2-DRExit2-IR11Update-DRAVR_RESET ($C)1Exit1-IR010Shift-IR101Update-IR010The AVR specific public JTAG instruction for setting the AVR device in the Reset modeor taking the device out from the Reset mode.
The TAP controller is not reset by thisinstruction. The one bit Reset Register is selected as Data Register. Note that the resetwill be active as long as there is a logic 'one' in the Reset Chain. The output from thischain is not latched.The active states are:•PROG_ENABLE ($4)Shift-DR: The Reset Register is shifted by the TCK input.The AVR specific public JTAG instruction for enabling programming via the JTAG port.The 16-bit Programming Enable Register is selected as data register.
The active statesare the following:•Shift-DR: the programming enable signature is shifted into the data register.•Update-DR: the programming enable signature is compared to the correct value,and Programming mode is entered if the signature is valid.3092467M–AVR–11/04PROG_COMMANDS ($5)PROG_PAGELOAD ($6)The AVR specific public JTAG instruction for entering programming commands via theJTAG port. The 15-bit Programming Command Register is selected as data register.The active states are the following:•Capture-DR: the result of the previous command is loaded into the data register.•Shift-DR: the data register is shifted by the TCK input, shifting out the result of theprevious command and shifting in the new command.•Update-DR: the programming command is applied to the Flash inputs.•Run-Test/Idle: one clock cycle is generated, executing the applied command.The AVR specific public JTAG instruction to directly load the Flash data page via theJTAG port.
The 2048-bit Virtual Flash Page Load Register is selected as data register.This is a virtual scan chain with length equal to the number of bits in one Flash page.Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR stateis not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the Shift-DR state by an internal statemachine.
This is the only active state:•Shift-DR: Flash page data are shifted in from TDI by the TCK input, andautomatically loaded into the Flash page one byte at a time.Note:PROG_PAGEREAD ($7)The AVR specific public JTAG instruction to read one full Flash data page via the JTAGport. The 2056-bit Virtual Flash Page Read Register is selected as data register. This isa virtual scan chain with length equal to the number of bits in one Flash page plus 8.Internally the Shift Register is 8-bit.
Unlike most JTAG instructions, the Capture-DRstate is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte by byte in the Shift-DR state by an internal statemachine. This is the only active state:•Shift-DR: Flash data are automatically read one byte at a time and shifted out onTDO by the TCK input.
The TDI input is ignored.Note:Data Registers310The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the firstdevice in JTAG scan chain. If the AVR cannot be the first device in the scan chain, thebyte-wise programming algorithm must be used.The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the firstdevice in JTAG scan chain. If the AVR cannot be the first device in the scan chain, thebyte-wise programming algorithm must be used.The data registers are selected by the JTAG instruction registers described in section“Programming Specific JTAG Instructions” on page 308. The data registers relevant forprogramming operations are:•Reset Register•Programming Enable Register•Programming Command Register•Virtual Flash Page Load Register•Virtual Flash Page Read RegisterATmega1282467M–AVR–11/04ATmega128Reset RegisterThe Reset Register is a Test Data Register used to reset the part during programming.
Itis required to reset the part before entering programming mode.A high value in the Reset Register corresponds to pulling the external Reset low. Thepart is reset as long as there is a high value present in the Reset Register. Dependingon the Fuse settings for the clock options, the part will remain reset for a Reset TimeOut Period (refer to “Clock Sources” on page 35) after releasing the Reset Register.
Theoutput from this Data Register is not latched, so the reset will take place immediately, asshown in Figure 123 on page 256.Programming Enable RegisterThe Programming Enable Register is a 16-bit register. The contents of this register iscompared to the programming enable signature, binary code 1010_0011_0111_0000.When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The Register is reset to 0 on Power-on Reset,and should always be reset when leaving Programming mode.Figure 147. Programming Enable RegisterTDIDATA$A370=DQProgramming enableClockDR & PROG_ENABLETDO3112467M–AVR–11/04Programming CommandRegisterThe Programming Command Register is a 15-bit register.
This register is used to serially shift in programming commands, and to serially shift out the result of the previouscommand, if any. The JTAG Programming Instruction Set is shown in Table 130. Thestate sequence when shifting in the programming commands is illustrated in Figure 149.Figure 148. Programming Command RegisterTDISTROBESADDRESS/DATAFlashEEPROMFusesLock BitsTDO312ATmega1282467M–AVR–11/04ATmega128Table 130.
JTAG Programming InstructionSet a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t careInstructionTDI sequenceTDO sequenceNotes1a. Chip erase0100011_100000000110001_100000000110011_100000000110011_10000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx1b. Poll for chip erase complete0110011_10000000xxxxxox_xxxxxxxx2a. Enter Flash Write0100011_00010000xxxxxxx_xxxxxxxx2b.
Load Address High Byte0000111_aaaaaaaaxxxxxxx_xxxxxxxx2c. Load Address Low Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx2d. Load Data Low Byte0010011_iiiiiiiixxxxxxx_xxxxxxxx2e. Load Data High Byte0010111_iiiiiiiixxxxxxx_xxxxxxxx2f. Latch Data0110111_000000001110111_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)2g. Write Flash Page0110111_000000000110101_000000000110111_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxxxxxxxxx_xxxxxxxx(1)2h. Poll for Page Write complete0110111_00000000xxxxxox_xxxxxxxx(2)3a. Enter Flash Read0100011_00000010xxxxxxx_xxxxxxxx3b. Load Address High Byte0000111_aaaaaaaaxxxxxxx_xxxxxxxx3c. Load Address Low Byte0000011_bbbbbbbbxxxxxxx_xxxxxxxx3d. Read Data Low and High Byte0110010_000000000110110_000000000110111_00000000xxxxxxx_xxxxxxxxxxxxxxx_ooooooooxxxxxxx_oooooooo4a.
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