ATmega128 (961723), страница 64
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The frequency will vary with package type and board layout.3232467M–AVR–11/04Two-wire Serial Interface CharacteristicsTable 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire SerialInterface meets or exceeds these requirements under the noted conditions.Timing symbols refer to Figure 153.Table 133. Two-wire Serial Bus RequirementsSymbolParameterVILVIHVhys(1)MinMaxUnitsInput Low-voltage-0.50.3 VCCVInput High-voltage0.7 VCCVCC + 0.5V–V0.4V20 + 0.1Cb(3)(2)300ns(3)(2)250ns(2)nsHysteresis of Schmitt Trigger InputsVOL(1)Output Low-voltagetr(1)Rise Time for both SDA and SCLtof(1)Output Fall Time from VIHmin to VILmaxtSP(1)Spikes Suppressed by Input FilterIiInput Current each I/O PinCi(1)Capacitance for each I/O PinSCL Clock FrequencyfSCLRpHold Time (repeated) START ConditiontLOWLow Period of the SCL ClocktHIGHHigh period of the SCL clocktSU;STASet-up time for a repeated START conditiontHD;DATData hold timetSU;DATData setup timetSU;STOSetup time for STOP conditiontBUFBus free time between a STOP and STARTcondition3240.05 VCC3 mA sink current1.2.3.4.(2)0(3)10 pF < Cb < 400 pF20 + 0.1Cb00.1 VCC < Vi < 0.9 VCC50-1010µA–10pF0400kHzfSCL ≤ 100 kHzV CC – 0,4V---------------------------3mA1000ns------------------CbΩfSCL > 100 kHzV CC – 0,4V---------------------------3mA300ns---------------CbΩfSCL ≤ 100 kHz4.0–µsfSCL > 100 kHz0.6–µs(6)fSCL ≤ 100 kHz4.7–µs(7)fSCL > 100 kHz1.3–µsfSCL ≤ 100 kHz4.0–µsfSCL > 100 kHz0.6–µsfSCL ≤ 100 kHz4.7–µsfSCL > 100 kHz0.6–µsfSCL ≤ 100 kHz03.45µsfSCL > 100 kHz00.9µsfSCL ≤ 100 kHz250–nsfSCL > 100 kHz100–nsfSCL ≤ 100 kHz4.0–µsfSCL > 100 kHz0.6–µsfSCL ≤ 100 kHz4.7–µsfCK(4)> max(16fSCL, 250kHz)Value of Pull-up resistortHD;STANotes:Condition(5)In ATmega128, this parameter is characterized and not 100% tested.Required only for fSCL > 100 kHz.Cb = capacitance of one bus line in pF.fCK = CPU clock frequencyATmega1282467M–AVR–11/04ATmega1285.
This requirement applies to all ATmega128 Two-wire Serial Interface operation. Otherdevices connected to the Two-wire Serial Bus need only obey the general fSCLrequirement.6. The actual low period generated by the ATmega128 Two-wire Serial Interface is(1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to bestrictly met at fSCL = 100 kHz.7. The actual low period generated by the ATmega128 Two-wire Serial Interface is(1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHzwhen fCK = 8 MHz.
Still, ATmega128 devices connected to the bus may communicateat full speed (400 kHz) with other ATmega128 devices, as well as any other devicewith a proper tLOW acceptance margin.Figure 153. Two-wire Serial Bus TimingtoftHIGHtLOWtrtLOWSCLtSU;STAtHD;STAtHD;DATtSU;DATtSU;STOSDAtBUFSPI TimingCharacteristicsSee Figure 154 and Figure 155 for details.Table 134. SPI Timing ParametersDescriptionMode1SCK periodMasterSee Table 722SCK high/lowMaster50% duty cycle3Rise/Fall timeMaster3.64SetupMaster105HoldMaster106Out to SCKMaster0.5 • tsck7SCK to outMaster108SCK to out highMaster109SS low to outSlave1510SCK periodSlave4 • tckSlave2 • tck11SCK high/low(1)Min12Rise/Fall timeSlave13SetupSlave1014HoldSlave1015SCK to outSlave16SCK to SS highSlave17SS high to tri-stateSlave18SS low to SCKSlaveNote:TypMaxns1.615µsns20102 • tck1.
In SPI Programming mode the minimum SCK high/low period is:- 2 tCLCL for fCK < 12 MHz- 3 tCLCL for fCK >12 MHz3252467M–AVR–11/04Figure 154. SPI Interface Timing Requirements (Master Mode)SS61SCK(CPOL = 0)22SCK(CPOL = 1)4MISO(Data Input)53MSB...LSB7MOSI(Data Output)MSB8...LSBFigure 155. SPI Interface Timing Requirements (Slave Mode)18SS10916SCK(CPOL = 0)1111SCK(CPOL = 1)13MOSI(Data Input)1412MSB...LSB1715MISO(Data Output)326MSB...LSBXATmega1282467M–AVR–11/04ATmega128ADC CharacteristicsTable 135.
ADC Characteristics, Single Ended ChannelsSymbolParameterConditionResolutionSingle Ended ConversionTyp(1)Units10Bits1.5LSBSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 1 MHz3.25LSBSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHzNoise Reduction mode1.5LSBSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 1 MHzNoise Reduction mode3.75LSBIntegral Non-Linearity (INL)Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz0.75LSBDifferential Non-Linearity (DNL)Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz0.5LSBGain ErrorSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz1LSBOffset errorSingle Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHz1LSBClock Frequency50Conversion Time13AVCCAnalog Supply VoltageVREFReference VoltageInput Voltage1000VINTInternal Voltage ReferenceRREFReference Input ResistanceRAINAnalog Input ResistancekHz260µs(3)(2)VCC - 0.3VCC + 0.3V2.0AVCCVGNDVREFV38.5kHz2.7VInput BandwidthNotes:Max(1)Single Ended ConversionVREF = 4V, VCC = 4VADC clock = 200 kHzAbsolute Accuracy(Including INL, DNL, Quantization Error, Gainand Offset Error)VINMin(1)2.3552.5632kΩ100MΩ1.
Values are guidelines only.2. Minimum for AVCC is 2.7V.3. Maximum for AVCC is 5.5V3272467M–AVR–11/04Table 136. ADC Characteristics, Differential ChannelsSymbolParameterMax(1)Units1x10BitsGain = 10x10BitsGain = 200x10BitsConditionGain =ResolutionAbsolute AccuracyIntegral Non-Linearity (INL)(Accuracy after Calibration for Offset andGain Error)Offset Error17LSBGain = 10xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz17LSBGain = 200xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz7LSBGain = 1xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz1.5LSBGain = 10xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz2LSBGain = 200xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz5LSB1x1.5%Gain = 10x1.5%Gain = 200x0.5%Gain = 1xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz2LSBGain = 10xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz3LSBGain = 200xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHz4LSBClock Frequency50200Conversion Time65260V2.0AVCC - 0.5VGNDVCCVInput Differential Voltage-VREF/GainVREF/GainVADC Conversion Output-511511LSBVREFReference VoltageInput VoltageInput Bandwidth328µsVCC + 0.3Analog Supply VoltageVDIFFkHz(3)AVCCVINTyp(1)Gain = 1xVREF = 4V, VCC = 5VADC clock = 50 - 200 kHzGain =Gain ErrorMin(1)VCC - 0.3(2)4kHzATmega1282467M–AVR–11/04ATmega128Table 136.
ADC Characteristics, Differential Channels (Continued)SymbolParameterVINTInternal Voltage ReferenceRREFReference Input ResistanceRAINAnalog Input ResistanceNotes:ConditionMin(1)Typ(1)Max(1)Units2.32.562.7V5532kΩ100MΩ1. Values are guidelines only.2. Minimum for AVCC is 2.7V.3. Maximum for AVCC is 5.5V.3292467M–AVR–11/04External Data Memory TimingTable 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state8 MHz OscillatorMinMaxVariable OscillatorSymbolParameterMinMaxUnit01/tCLCLOscillator Frequency0.016MHz1tLHLLALE Pulse Width1151.0tCLCL-10ns2tAVLLAddress Valid A to ALE Low57.50.5tCLCL-5(1)ns3atLLAX_STAddress Hold After ALE Low,write access553btLLAX_LDAddress Hold after ALE Low,read access55nsns(1)4tAVLLCAddress Valid C to ALE Low57.50.5tCLCL-5ns5tAVRLAddress Valid to RD Low1151.0tCLCL-10ns6tAVWLAddress Valid to WR Low1151.0tCLCL-10ns7tLLWLALE Low to WR Low47.58tLLRLALE Low to RD Low9tDVRHData Setup to RD High10tRLDVRead Low to Data Valid11tRHDXData Hold After RD High12tRLRHRD Pulse Width47.567.50.5tCLCL-15(2)0.5tCLCL+5(2)ns67.5(2)(2)ns400.5tCLCL-150.5tCLCL+540ns751.0tCLCL-50001151.0tCLCL-10nsns13tDVWLData Setup to WR Low42.514tWHDXData Hold After WR High1151.0tCLCL-10ns15tDVWHData Valid to WR High1251.0tCLCLns16tWLWHWR Pulse Width1151.0tCLCL-10nsNotes:0.5tCLCL-20ns(1)ns1.
This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state8 MHz OscillatorSymbolParameter01/tCLCLOscillator Frequency10tRLDVRead Low to Data Valid12tRLRHRD Pulse Width2402.0tCLCL-10ns15tDVWHData Valid to WR High2402.0tCLCLns16tWLWHWR Pulse Width2402.0tCLCL-10ns330MinMaxVariable OscillatorMinMaxUnit0.016MHz2002.0tCLCL-50nsATmega1282467M–AVR–11/04ATmega128Table 139.
External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 04 MHz OscillatorMinMaxVariable OscillatorSymbolParameterMinMaxUnit01/tCLCLOscillator Frequency0.016MHz10tRLDVRead Low to Data Valid12tRLRHRD Pulse Width3653.0tCLCL-10ns15tDVWHData Valid to WR High3753.0tCLCLns16tWLWHWR Pulse Width3653.0tCLCL-10ns3253.0tCLCL-50nsTable 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 14 MHz OscillatorMinMaxVariable OscillatorSymbolParameterMinMaxUnit01/tCLCLOscillator Frequency0.016MHz10tRLDVRead Low to Data Valid12tRLRHRD Pulse Width3653.0tCLCL-10ns14tWHDXData Hold After WR High2402.0tCLCL-10ns15tDVWHData Valid to WR High3753.0tCLCLns16tWLWHWR Pulse Width3653.0tCLCL-10ns3253.0tCLCL-50nsTable 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state4 MHz OscillatorMinMaxVariable OscillatorSymbolParameterMinMaxUnit01/tCLCLOscillator Frequency0.08MHz1tLHLLALE Pulse Width235tCLCL-15ns2tAVLLAddress Valid A to ALE Low1150.5tCLCL-10(1)ns3atLLAX_STAddress Hold After ALE Low,write access553btLLAX_LDAddress Hold after ALE Low,read access55ns(1)4tAVLLCAddress Valid C to ALE Low1155tAVRLAddress Valid to RD Low2351.0tCLCL-156tAVWLAddress Valid to WR Low2351.0tCLCL-157tLLWLALE Low to WR Low1158tLLRLALE Low to RD Low1159tDVRHData Setup to RD High4510tRLDVRead Low to Data Valid11tRHDXData Hold After RD High0.5tCLCL-10ns1301300.5tCLCL-10(2)0.5tCLCL-10(2)nsns0.5tCLCL+5(2)ns0.5tCLCL+5(2)ns451900nsns1.0tCLCL-600nsns3312467M–AVR–11/04Table 141.
External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)4 MHz Oscillator12SymbolParameterMintRLRHRD Pulse Width235MaxVariable OscillatorMinMax1.0tCLCL-15Unitns(1)13tDVWLData Setup to WR Low10514tWHDXData Hold After WR High2351.0tCLCL-15ns15tDVWHData Valid to WR High2501.0tCLCLns16tWLWHWR Pulse Width2351.0tCLCL-15nsNotes:0.5tCLCL-20ns1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.2.
This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 14 MHz OscillatorMinMaxVariable OscillatorSymbolParameterMinMaxUnit01/tCLCLOscillator Frequency0.08MHz10tRLDVRead Low to Data Valid12tRLRHRD Pulse Width4852.0tCLCL-15ns15tDVWHData Valid to WR High5002.0tCLCLns16tWLWHWR Pulse Width4852.0tCLCL-15ns4402.0tCLCL-60nsTable 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 04 MHz OscillatorMinMaxVariable OscillatorSymbolParameterMinMaxUnit01/tCLCLOscillator Frequency0.08MHz10tRLDVRead Low to Data Valid12tRLRHRD Pulse Width7353.0tCLCL-15ns15tDVWHData Valid to WR High7503.0tCLCLns16tWLWHWR Pulse Width7353.0tCLCL-15ns6903.0tCLCL-60nsTable 144.
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