ATmega128 (961723), страница 67

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For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesshould never be written.2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate onall bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructionswork with registers $00 to $1F only.ATmega1282467M–AVR–11/04ATmega128Instruction Set SummaryMnemonicsOperandsDescriptionOperationFlags#ClocksARITHMETIC AND LOGIC INSTRUCTIONSADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,HADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1SUBIRd, KSubtract Constant from RegisterRd ← Rd - KZ,C,N,V,H1SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V11COMRdOne’s ComplementRd ← $FF − RdZ,C,N,V1NEGRdTwo’s ComplementRd ← $00 − RdZ,C,N,V,H1SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1CBRRd,KClear Bit(s) in RegisterRd ← Rd • ($FF - K)Z,N,V1INCRdIncrementRd ← Rd + 1Z,N,V1DECRdDecrementRd ← Rd − 1Z,N,V1TSTRdTest for Zero or MinusRd ← Rd • RdZ,N,V1CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1SERRdSet RegisterRd ← $FFNone1MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) <<1R1:R0 ← (Rd x Rr) << 1R1:R0 ← (Rd x Rr) << 1Z,C2Z,C2Z,C22FMULSRd, RrFractional Multiply SignedFMULSURd, RrFractional Multiply Signed with UnsignedBRANCH INSTRUCTIONSRJMPkIJMPRelative JumpPC ← PC + k + 1NoneIndirect Jump to (Z)PC ← ZNone2JMPkDirect JumpPC ← kNone3RCALLkRelative Subroutine CallPC ← PC + k + 1None3Indirect Call to (Z)PC ← ZNone3Direct Subroutine CallPC ← kNone4RETSubroutine ReturnPC ← STACKNone4RETIInterrupt ReturnPC ← STACKI4ICALLCALLkCPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3NoneCPRd,RrCompareRd − RrZ, N,V,C,H1CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,HSBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3None1/2/311/2/3SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3None1/2/3SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2BREQkBranch if Equalif (Z = 1) then PC ← PC + k + 1None1/2BRNEkBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2BRCSkBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2BRCCkBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2BRSHkBranch if Same or Higherif (C = 0) then PC ← PC + k + 1None1/2BRLOkBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2BRMIkBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2BRPLkBranch if Plusif (N = 0) then PC ← PC + k + 1None1/2BRGEkBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2BRLTkBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2BRHSkBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2BRHCkBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2BRTSkBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2BRTCkBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2BRVSkBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2BRVCkBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/23672467M–AVR–11/04Instruction Set Summary (Continued)MnemonicsOperandsDescriptionOperationFlagsBRIEkBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None#Clocks1/2BRIDkBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2Rd ← RrRd+1:Rd ← Rr+1:RrNone1None11DATA TRANSFER INSTRUCTIONSMOVRd, RrMove Between RegistersMOVWRd, RrCopy Register WordLDIRd, KLoad ImmediateRd ← KNoneLDRd, XLoad IndirectRd ← (X)None2LDRd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None2LDRd, - XLoad Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None2LDRd, YLoad IndirectRd ← (Y)None2LDRd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None2LDRd, - YLoad Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None2LDDRd,Y+qLoad Indirect with DisplacementRd ← (Y + q)None2LDRd, ZLoad IndirectRd ← (Z)None2LDRd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None2LDRd, -ZLoad Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None2LDDRd, Z+qLoad Indirect with DisplacementRd ← (Z + q)None2LDSRd, kLoad Direct from SRAMRd ← (k)None2STX, RrStore Indirect(X) ← RrNone2STX+, RrStore Indirect and Post-Inc.(X) ← Rr, X ← X + 1None2ST- X, RrStore Indirect and Pre-Dec.X ← X - 1, (X) ← RrNone2STY, RrStore Indirect(Y) ← RrNone2STY+, RrStore Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None2ST- Y, RrStore Indirect and Pre-Dec.Y ← Y - 1, (Y) ← RrNone2STDY+q,RrStore Indirect with Displacement(Y + q) ← RrNone2STZ, RrStore Indirect(Z) ← RrNone2STZ+, RrStore Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None2ST-Z, RrStore Indirect and Pre-Dec.Z ← Z - 1, (Z) ← RrNone2STDZ+q,RrStore Indirect with Displacement(Z + q) ← RrNone2STSk, RrStore Direct to SRAM(k) ← RrNone2Load Program MemoryR0 ← (Z)None3LPMLPMRd, ZLoad Program MemoryRd ← (Z)None3LPMRd, Z+Load Program Memory and Post-IncRd ← (Z), Z ← Z+1None33Extended Load Program MemoryR0 ← (RAMPZ:Z)NoneELPMRd, ZExtended Load Program MemoryRd ← (RAMPZ:Z)None3ELPMRd, Z+Extended Load Program Memory and Post-IncRd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1None3Store Program Memory(Z) ← R1:R0None-INRd, PIn PortRd ← PNone1OUTP, RrOut PortP ← RrNone1PUSHRrPush Register on StackSTACK ← RrNone2POPRdPop Register from StackRd ← STACKNone2ELPMSPMBIT AND BIT-TEST INSTRUCTIONSSBIP,bSet Bit in I/O RegisterI/O(P,b) ← 1None2CBIP,bClear Bit in I/O RegisterI/O(P,b) ← 0None2LSLRdLogical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1LSRRdLogical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1ROLRdRotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Z,C,N,V1RORRdRotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z,C,N,V1ASRRdArithmetic Shift RightRd(n) ← Rd(n+1), n=0..6Z,C,N,V1SWAPRdSwap NibblesRd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None1BSETsFlag SetSREG(s) ← 1SREG(s)1BCLRsFlag ClearSREG(s) ← 0SREG(s)1BSTRr, bBit Store from Register to TT ← Rr(b)T1BLDRd, bBit load from T to RegisterRd(b) ← TNone1SECSet CarryC←1C1CLCClear CarryC←0C1SENSet Negative FlagN←1N1CLNClear Negative FlagN←0N1SEZSet Zero FlagZ←1Z1CLZClear Zero FlagZ←0Z1SEIGlobal Interrupt EnableI←1I1CLIGlobal Interrupt DisableI←0I1SESSet Signed Test FlagS←1S1CLSClear Signed Test FlagS←0S1368ATmega1282467M–AVR–11/04ATmega128Instruction Set Summary (Continued)DescriptionOperationFlagsSEVMnemonicsOperandsSet Twos Complement Overflow.V←1V#Clocks1CLVClear Twos Complement OverflowV←0V1SETSet T in SREGT←1T1CLTClear T in SREGT←0T1SEHCLHSet Half Carry Flag in SREGClear Half Carry Flag in SREGH←1H←0HH11MCU CONTROL INSTRUCTIONSNOPNo OperationNone1SLEEPSleep(see specific descr.

for Sleep function)None1WDRBREAKWatchdog ResetBreak(see specific descr. for WDR/timer)For On-chip Debug OnlyNoneNone1N/A3692467M–AVR–11/04Ordering InformationSpeed (MHz)816Notes:Power Supply2.7 - 5.5V4.5 - 5.5VOrdering CodePackage(1)ATmega128L-8ACATmega128L-8MC64A64M1Commercial(0oC to 70oC)ATmega128L-8AIATmega128L-8AU(2)ATmega128L-8MIATmega128L-8MU(2)64A64A64M164M1Industrial(-40oC to 85oC)ATmega128-16ACATmega128-16MC64A64M1Commercial(0oC to 70oC)ATmega128-16AIATmega128-16AU(2)ATmega128-16MIATmega128-16MU(2)64A64A64M164M1Industrial(-40oC to 85oC)Operation Range1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities.2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).

Also Halide free and fully Green.Package Type64A64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)64M164-pad, 9 x 9 x 1.0 mm, Micro Lead Frame Package (MLF)370ATmega1282467M–AVR–11/04ATmega128Packaging Information64APIN 1BPIN 1 IDENTIFIERE1eED1DC0˚~7˚A1A2ALCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLNotes:1. This package conforms to JEDEC reference MS-026, Variation AEB.2. Dimensions D1 and E1 do not include mold protrusion.

Allowableprotrusion is 0.25 mm per side. Dimensions D1 and E1 are maximumplastic body size dimensions including mold mismatch.3. Lead coplanarity is 0.10 mm maximum.MINNOMMAXA––1.20A10.05–0.15A20.951.001.05D15.7516.0016.25D113.9014.0014.10E15.7516.0016.25E113.9014.0014.10B0.30–0.45C0.09–0.20L0.45–0.75eNOTENote 2Note 20.80 TYP10/5/2001R2325 Orchard ParkwaySan Jose, CA 95131TITLE64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)DRAWING NO.REV.64AB3712467M–AVR–11/0464M1DMarked Pin# 1 IDECSEATING PLANEA1TOP VIEWAK0.08 CLPin #1 CornerD2123Option ASIDE VIEWPin #1TriangleCOMMON DIMENSIONS(Unit of Measure = mm)E2Option BPin #1Chamfer(C 0.30)SYMBOLMINNOMMAXA0.800.901.00–0.020.050.230.250.28A1bDKOption CbeD2Pin #1Notch(0.20 R)BOTTOM VIEWNote: JEDEC Standard MO-220, (SAW Singulation) Fig.

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