ATmega128 (961723), страница 69
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Stabilizing time needed when changing OSCCAL RegisterAfter increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructionsincorrectly.Problem Fix / WorkaroundThe behavior follows errata number 1., and the same Fix / Workaround is applicableon this errata.A proposal for solving problems regarding the JTAG instruction IDCODE is presentedbelow.IDCODE masks data from TDI inputThe public but optional JTAG instruction IDCODE is not implemented correctlyaccording to IEEE1149.1; a logic one is scanned into the shift register instead of theTDI input while shifting the Device ID Register.
Hence, captured data from the pre-3772467M–AVR–11/04ceding devices in the boundary scan chain are lost and replaced by all-ones, anddata to succeeding devices are replaced by all-ones during Update-DR.If ATmega128 is the only device in the scan chain, the problem is not visible.Problem Fix / WorkaroundSelect the Device ID Register of the ATmega128 (Either by issuing the IDCODEinstruction or by entering the Test-Logic-Reset state of the TAP controller) to readout the contents of its Device ID Register and possibly data from succeedingdevices of the scan chain. Note that data to succeeding devices cannot be enteredduring this scan, but data to preceding devices can. Issue the BYPASS instructionto the ATmega128 to select its Bypass Register while reading the Device ID Registers of preceding devices of the boundary scan chain.
Never read data fromsucceeding devices in the boundary scan chain or upload data to the succeedingdevices while the Device ID Register is selected for the ATmega128. Note that theIDCODE instruction is the default instruction selected by the Test-Logic-Reset stateof the TAP-controller.Alternative Problem Fix / WorkaroundIf the Device IDs of all devices in the boundary scan chain must be captured simultaneously (for instance if blind interrogation is used), the boundary scan chain canbe connected in such way that the ATmega128 is the fist device in the chain.Update-DR will still not work for the succeeding devices in the boundary scan chainas long as IDCODE is present in the JTAG Instruction Register, but the Device IDregistered cannot be uploaded in any case.378ATmega1282467M–AVR–11/04ATmega128Datasheet RevisionHistoryPlease note that the referring page numbers in this section are referred to this document.
The referring revision in this section are referring to the document revision.Changes from Rev.2467L-05/04 to Rev.2467M-11/041. Removed “analog ground”, replaced by “ground”.2. Updated Table 11 on page 38, Table 114 on page 287, Table 128 on page 306,and Table 132 on page 323. Updated Figure 114 on page 239.3. Added note to “Port C (PC7..PC0)” on page 6.4. Updated “Ordering Information” on page 370.Changes from Rev.2467K-03/04 to Rev.2467L-05/041. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrencesof ICx with ICPx.2. Updated Table 8 on page 36, Table 19 on page 48, Table 22 on page 54, Table96 on page 243, Table 126 on page 302, Table 128 on page 306, Table 132 onpage 323, and Table 134 on page 325.3.
Updated “External Memory Interface” on page 24.4. Updated “Device Identification Register” on page 255.5. Updated “Electrical Characteristics” on page 321.6. Updated “ADC Characteristics” on page 327.7. Updated “ATmega128 Typical Characteristics” on page 335.8. Updated “Ordering Information” on page 370.Changes from Rev.2467J-12/03 to Rev.2467K-03/041. Updated “Errata” on page 373.Changes from Rev.2467I-09/03 to Rev.2467J-12/031. Updated “Calibrated Internal RC Oscillator” on page 39.Changes from Rev.2467H-02/03 to Rev.2467I-09/031. Updated note in “XTAL Divide Control Register – XDIV” on page 41.2. Updated “JTAG Interface and On-chip Debug System” on page 46.3. Updated values for VBOT (BODLEVEL = 1) in Table 19 on page 48.4.
Updated “Test Access Port – TAP” on page 248 regarding JTAGEN.5. Updated description for the JTD bit on page 257.6. Added a note regarding JTAGEN fuse to Table 118 on page 290.3792467M–AVR–11/047. Updated RPU values in “DC Characteristics” on page 321.8. Added a proposal for solving problems regarding the JTAG instructionIDCODE in “Errata” on page 373.Changes from Rev.2467G-09/02 to Rev.2467H-02/031. Corrected the names of the two Prescaler bits in the SFIOR Register.2. Added Chip Erase as a first step under “Programming the Flash” on page 318and “Programming the EEPROM” on page 319.3.
Removed reference to the “Multipurpose Oscillator” application note and the“32 kHz Crystal Oscillator” application note, which do not exist.4. Corrected OCn waveforms in Figure 52 on page 123.5. Various minor Timer1 corrections.6. Added information about PWM symmetry for Timer0 and Timer2.7. Various minor TWI corrections.8.
Added reference to Table 124 on page 293 from both SPI Serial Programmingand Self Programming to inform about the Flash Page size.9. Added note under “Filling the Temporary Buffer (Page Loading)” on page 282about writing to the EEPROM during an SPM Page load.10. Removed ADHSM completely.11. Added section “EEPROM Write During Power-down Sleep Mode” on page 23.12. Updated drawings in “Packaging Information” on page 371.Changes from Rev.2467F-09/02 to Rev.2467G-09/021. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.Changes from Rev.2467E-04/02 to Rev.2467F-09/021.
Added 64-pad MLF Package and updated “Ordering Information” on page 370.2. Added the section “Using all Locations of External Memory Smaller than 64KB” on page 31.3. Added the section “Default Clock Source” on page 35.4. Renamed SPMCR to SPMCSR in entire document.5. When using external clock there are some limitations regards to change offrequency. This is descried in “External Clock” on page 40 and Table 131,“External Clock Drive,” on page 323.6.
Added a sub section regarding OCD-system and power consumption in thesection “Minimizing Power Consumption” on page 45.380ATmega1282467M–AVR–11/04ATmega1287. Corrected typo (WGM-bit setting) for:“Fast PWM Mode” on page 96 (Timer/Counter0).“Phase Correct PWM Mode” on page 98 (Timer/Counter0).“Fast PWM Mode” on page 150 (Timer/Counter2).“Phase Correct PWM Mode” on page 152 (Timer/Counter2).8.
Corrected Table 81 on page 192 (USART).9. Corrected Table 102 on page 261 (Boundary-Scan)10. Updated Vil parameter in “DC Characteristics” on page 321.Changes from Rev.2467D-03/02 to Rev.2467E-04/021. Updated the Characterization Data in Section “ATmega128 Typical Characteristics” on page 335.2. Updated the following tables:Table 19 on page 48, Table 20 on page 52, Table 68 on page 157, Table 102 onpage 261, and Table 136 on page 328.3. Updated Description of OSCCAL Calibration Byte.In the data sheet, it was not explained how to take advantage of the calibrationbytes for 2, 4, and 8 MHz Oscillator selections.
This is now added in the followingsections:Improved description of “Oscillator Calibration Register – OSCCAL” on page 39 and“Calibration Byte” on page 291.Changes from Rev.2467C-02/02 to Rev.2467D-03/021. Added more information about “ATmega103 Compatibility Mode” on page 5.2. Updated Table 2, “EEPROM Programming Time,” on page 21.3.
Updated typical Start-up Time in Table 7 on page 35, Table 9 and Table 10 onpage 37, Table 12 on page 38, Table 14 on page 39, and Table 16 on page 40.4. Updated Table 22 on page 54 with typical WDT Time-out.5. Corrected description of ADSC bit in “ADC Control and Status Register A –ADCSRA” on page 245.6. Improved description on how to do a polarity check of the ADC differentialresults in “ADC Conversion Result” on page 242.7. Corrected JTAG version numbers in “JTAG Version Numbers” on page 256.8. Improved description of addressing during SPM (usage of RAMPZ) on“Addressing the Flash During Self-Programming” on page 280, “PerformingPage Erase by SPM” on page 282, and “Performing a Page Write” on page282.9. Added not regarding OCDEN Fuse below Table 118 on page 290.10.
Updated Programming Figures:3812467M–AVR–11/04Figure 135 on page 292 and Figure 144 on page 304 are updated to also reflect thatAVCC must be connected during Programming mode. Figure 139 on page 299added to illustrate how to program the fuses.11. Added a note regarding usage of thePROG_PAGEREAD instructions on page 310.PROG_PAGELOAD12. Added Calibrated RC Oscillator characterization“ATmega128 Typical Characteristics” on page 335.curvesinandsection13. Updated “Two-wire Serial Interface” section.More details regarding use of the TWI Power-down operation and using the TWI asmaster with low TWBRR values are added into the data sheet.
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